IDT72V265LA15TFI IDT, Integrated Device Technology Inc, IDT72V265LA15TFI Datasheet - Page 21

IC FIFO SS 16384X18 15NS 64STQFP

IDT72V265LA15TFI

Manufacturer Part Number
IDT72V265LA15TFI
Description
IC FIFO SS 16384X18 15NS 64STQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V265LA15TFI

Function
Synchronous
Memory Size
288K (16K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-STQFP
Configuration
Dual
Density
288Kb
Access Time (max)
10ns
Word Size
18b
Organization
16Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
STQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V265LA15TFI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V265LA15TFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V265LA15TFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
3. OE = LOW
4. W
5. OR goes LOW at 60 ns + 2 RCLK cycles + t
WCLK
NOTE:
1. X = 12 for the IDT72V255LA and X = 13 for the IDT72V265LA.
8,192 x 18, 16,384 x 18
Q
WCLK
procedure. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
SEN
RCLK
0
WEN
REN
LD
1
PAE
PAF
- Q
SI
, W
OR
RT
HF
2
n
, W
t
3
ENS
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
LDS
t
ENS
DS
t
ENS
t
RTS
t
RTS
REF
t
t
ENH
LDH
.
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW4
1
Figure 12. Retransmit Timing (FWFT Mode)
2
t
PAF
1
W
x+1
BIT X
21
(1)
BIT 0
2
t
PAE
FULL OFFSET
3
COMMERCIAL AND INDUSTRIAL
t
A
t
ENH
t
REF
(5)
TEMPERATURE RANGES
W
1
(4)
BIT X
OCTOBER 22, 2008
t
t
t
t
LDH
LDH
LDH
ENH
(1)
W
4
2
t
A
4672 drw 16
t
ENH
4672 drw15
W
3

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