IDT72V265LA15TFI IDT, Integrated Device Technology Inc, IDT72V265LA15TFI Datasheet - Page 27

• Manufacturer Part Number: IDT72V265LA15TFI
• Description: IC FIFO SS 16384X18 15NS 64STQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V265LA15TFI

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V265LA15TFI

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is t
3. Tf is the period of the ‘selected clock’.
4. T
5. Typical I
DIFFERENCES BETWEEN THE IDT72V255LA/72V265LA AND IDT72V255L/72V265L
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RCLK
IDT has improved the performance of the IDT72V255/72V265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part
is the cycle period of the read clock.
SKEW3
CC1
Pin #3
First Word Latency
(IDT Standard Mode)
First Word Latency
(FWFT Mode)
Retransmit Latency
(IDT Standard Mode)
Retransmit Latency
(FWFT Mode)
I
I
Typical I
CC1
CC2
is based on V
.
Item
CC1
(5)
CC
= 3.3V, t
A
= 25°C, f
DC (Don’t Care) - There is
no restriction on WCLK and
RCLK. See note 1.
60ns
60ns
60ns
60ns
55mA
20mA
10 + 1.1*f
3.3 VOLT CMOS SuperSync FIFO
8,192 x 18
16,384 x 18
(2)
(2)
(2)
(2)
+ t
+ t
+ t
+ t
S
IDT72V255LA
IDT72V265LA
NEW PART
S
= WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at f
REF
REF
REF
REF
+ 0.02*C
+ 1 T
+ 2 T
+ 1 T
+ 2 T
RCLK
RCLK
RCLK
RCLK
L
*f
S
(mA)
(4)
(4)
(4)
(4)
FS (Frequency Select)
t
t
t
t
10mA
Not Given
100mA
FWL
FWL
RTF
RTF
27
1
2
1
2
= 14*Tf
= 14*Tf
= 10*Tf
= 10*Tf
ADDENDUM
IDT72V255L
IDT72V265L
OLD PART
(3)
(3)
(3)
(3)
+ 3T
+ 4T
+ 2T
+ 3T
™
RCLK
RCLK
RCLK
RCLK
(4)
(4)
(4)
(4)
(ns)
(ns)
(ns)
(ns)
In the LA part this pin must be tied
to either V
not toggle after reset.
First word latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
First word latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Active supply current
Standby current
Typical I
CC1
Comments
CC
Current calculation
S
or GND and must
/2, C
L
= Capacitive Load (in pF).
IDT72V255LA
IDT72V265LA