IDT72V265LA15TFI IDT, Integrated Device Technology Inc, IDT72V265LA15TFI Datasheet - Page 14

• Manufacturer Part Number: IDT72V265LA15TFI
• Description: IC FIFO SS 16384X18 15NS 64STQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V265LA15TFI

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V265LA15TFI

EMPTY FLAG (EF/OR)
(EF) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not empty.
See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing
(IDT Standard Mode), for the relevant timing information.
LOW at the same time that the first word written to an empty FIFO appears
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition
that shifts the last word from the FIFO memory to the outputs. OR goes
HIGH only with a true read (RCLK with REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The PAF will go LOW after (8,192-m) writes for the
IDT72V255LA and (16,384-m) writes for the IDT72V265LA. The offset “m”
is the full offset value. The default setting for this value is stated in the
footnote of Table 1.
IDT72V255LA and (16,385-m) writes for the IDT72V265LA, where m is the
full offset value. The default setting for this value is stated in the footnote of
Table 2.
and FWFT Mode), for the relevant timing information.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
In FWFT mode, the Output Ready (OR) function is selected. OR goes
In IDT Standard mode, EF is a double register-buffered output. In FWFT
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
In FWFT mode, the PAF will go LOW after (8,193-m) writes for the
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
PAF is synchronous and updated on the rising edge of WCLK.
EF/OR is synchronous and updated on the rising edge of RCLK.
14
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go
LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
dard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
FIFO beyond half-full sets HF LOW. The flag remains LOW until the differ-
ence between the write and read pointers becomes less than or equal to
half of the total depth of the device; the rising RCLK edge that accomplishes
this condition sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 8,192
for the IDT72V255LA and 16,384 for the IDT72V265LA.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 8,193 for the
IDT72V255LA and 16,385 for the IDT72V265LA.
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
17
) are data outputs for 18-bit wide data.
0
-Q
17
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008