IDT72V265LA15TFI IDT, Integrated Device Technology Inc, IDT72V265LA15TFI Datasheet - Page 25

• Manufacturer Part Number: IDT72V265LA15TFI
• Description: IC FIFO SS 16384X18 15NS 64STQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V265LA15TFI

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V265LA15TFI

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 8,192 and 16,384 for the IDT72V265LA with an 18-bit bus
width. In FWFT mode, the FIFOs can be connected in series (the data
outputs of one FIFO connected to the data inputs of the next) with no
external logic necessary. The resulting configuration provides a total
depth equivalent to the sum of the depths associated with each single
FIFO. Figure 24 shows a depth expansion using two IDT72V255LA/
72V265LA devices.
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down")
until it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO's outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
RCLK period. Note that extra cycles should be added for the possibility
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
The IDT72V255LA can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all
For an empty expansion configuration, the amount of time it takes for OR
where N is the number of FIFOs in the expansion and T
DATA IN
FWFT/SI
WRITE CLOCK
WRITE ENABLE
INPUT READY
n
(N – 1)*(4*transfer clock) + 3*T
Dn
WEN
IR
WCLK
Figure 20. Block Diagram of 16,384 x 18 and 32,768 x 18 Depth Expansion
72V255LA
72V265LA
FWFT/SI
IDT
TRANSFER CLOCK
RCLK
RCLK
REN
OR
OE
Qn
RCLK
is the
GND
25
n
that the t
or RCLK and transfer clock, for the OR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
WCLK period. Note that extra cycles should be added for the possibility
that the tSKEW1 specification is not met between RCLK and transfer clock,
or WCLK and transfer clock, for the IR flag.
ever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
The "ripple down" delay is only noticeable for the first word written to an
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the
where N is the number of FIFOs in the expansion and T
The Transfer Clock line should be tied to either WCLK or RCLK, which-
SKEW3
specification is not met between WCLK and transfer clock,
WCLK
IR
WEN
Dn
(N – 1)*(3*transfer clock) + 2 T
72V255LA
72V265LA
FWFT/SI
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
TEMPERATURE RANGES
OR
Qn
OE
WCLK
OCTOBER 22, 2008
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
READ CLOCK
DATA OUT
4672 drw 23
WCLK
is the