AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet

Page 1

... The AD9517-1 is specified for operation over the industrial range of −40°C to +85°C. 1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-1 is used referring to that specific member of the AD9517 family. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © ...

Page 2

... AD9517-1 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 6 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 8 Clock Output Absolute Phase Noise (Internal VCO Used).... 9 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ...

Page 3

... MSB/LSB First Transfers ............................................................53 REVISION HISTORY 7/07—Revision 0: Initial Version Register Map Overview ..................................................................56 Register Map Descriptions.............................................................60 Application Notes............................................................................78 Using the AD9517 Outputs for ADC Clock Applications ....78 LVPECL Clock Distribution......................................................78 LVDS Clock Distribution...........................................................78 CMOS Clock Distribution.........................................................79 Outline Dimensions........................................................................80 Ordering Guide ...........................................................................80 Rev Page AD9517-1 ...

Page 4

... AD9517-1 SPECIFICATIONS Typical (typ) is given for 3.3 V ± 5 S_LVPECL unless otherwise noted. Minimum (min) and maximum (max) values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ V 3.135 3 2.375 S_LVPECL RSET Pin Resistor 4.12 CPRSET Pin Resistor 5 ...

Page 5

... Rev Page AD9517-1 Test Conditions/Comments Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns 0x17<1:0> = 01b 0x17<1:0> = 00b; 0x17<1:0> = 11b 0x17<1:0> = 10b Programmable With CP = 5.1 kΩ RSET 0.5 < ...

Page 6

... AD9517-1 Parameter 2 PLL DIGITAL LOCK DETECT WINDOW Required to Lock (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns Unlock After Lock (Hysteresis) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) 1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. ...

Page 7

... Rev Page AD9517-1 Test Conditions/Comments Single-ended; termination = 10 pF See Figure load @ 1 mA load Test Conditions/Comments Termination = 50 Ω − level = 810 mV S 20% to 80%, measured differentially 80% to 20%, measured differentially See Figure 42 See Figure 44 Termination = 100 Ω differential; 3.5 mA ...

Page 8

... AD9517-1 Parameter Delay Variation with Temperature 5 Short Delay Range Zero Scale Full Scale Long Delay Range 5 Zero Scale Full Scale 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to A for noninverting, and B for inverting. ...

Page 9

... Rev Page AD9517-1 Test Conditions/Comments Input slew rate > 1 V/ns Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns Input slew rate > 1 V/ns Test Conditions/Comments Internal VCO; direct to LVPECL output ...

Page 10

... AD9517-1 Parameter VCO = 2.3 GHz; OUTPUT = 2.3 GHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER VCO = 2.46 GHz; LVPECL = 491.52 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz ...

Page 11

... Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 350 f rms Calculated from SNR of ADC method S Rev Page AD9517-1 Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal rms kHz to 20 MHz S ...

Page 12

... AD9517-1 DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 000000 Delay (1600 μA, 1C) Fine Adj. 101111 Delay (800 μA, 1C) Fine Adj. 000000 Delay (800 μA, 1C) Fine Adj. 101111 Delay (800 μA, 4C) Fine Adj. 000000 Delay (800 μ ...

Page 13

... On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor 1.02 MHz Frequency above which the monitor indicates the presence of the reference 8 kHz Frequency above which the monitor indicates the presence of the reference 1.6 V 260 mV Rev Page AD9517-1 ...

Page 14

... AD9517-1 POWER DISSIPATION Table 17. Parameter POWER DISSIPATION, CHIP Power-On Default Full Operation; CMOS Outputs at 206 MHz Full Operation; LVDS Outputs at 206 MHz PD Power-Down PD Power-Down, Maximum Sleep V Supply CP POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider REFIN (Differential) REF1, REF2 (Single-Ended) VCO PLL Channel Divider ...

Page 15

... LVDS t CMOS Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential t FP Rev Page DIFFERENTIAL 80% LVDS 20 Figure 4. LVDS Timing, Differential SINGLE-ENDED 80% CMOS 10pF LOAD 20 Figure 5. CMOS Timing, Single-Ended Load AD9517-1 ...

Page 16

... AD9517-1 ABSOLUTE MAXIMUM RATINGS Table 18. With Parameter or Pin Respect To VS, VS_LVPECL GND VCP GND REFIN, REFIN GND REFIN REFIN RSET GND CPRSET GND CLK, CLK GND CLK CLK SCLK, SDIO, SDO, CS GND OUT0, OUT0, OUT1, OUT1, GND OUT2, OUT2, OUT3, OUT3, ...

Page 17

... AD9517-1 6 TOP VIEW SYNC 7 (Not to Scale CLK 11 CLK 12 Figure 6. Pin Configuration < Rev Page OUT4 (OUT4A) 35 OUT4 (OUT4B) 34 OUT5 (OUT5A) 33 OUT5 (OUT5B OUT7 (OUT7B) 29 OUT7 (OUT7A) 28 OUT6 (OUT6B) 27 OUT6 (OUT6A < 5.0 V. AD9517-1 ...

Page 18

... AD9517-1 Pin No. Mnemonic Description 20 OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 22 OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 23 OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 35 OUT4 (OUT4A) LVDS/CMOS Output; One Side of a Differential LVDS Output Single-Ended CMOS Output. ...

Page 19

... Rev Page 2.3 2.4 2.5 2.6 VCO FREQUENCY (GHz) Figure 10. VCO K vs. Frequency VCO 5.0 4.5 4.0 3.5 PUMP DOWN PUMP UP 3.0 2.5 2.0 1.5 1.0 0 0.5 1.0 1.5 2.0 2.5 VOLTAGE ON CP PIN (V) Figure 11. Charge Pump Characteristics @ V 5.0 4.5 4.0 3.5 PUMP DOWN PUMP UP 3.0 2.5 2.0 1.5 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 12. Charge Pump Characteristics @ V AD9517-1 2.7 3 4.0 4.5 5 ...

Page 20

... AD9517-1 –140 –145 –150 –155 –160 –165 –170 0.1 1 PFD FREQUENCY (MHz) Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency –210 –212 –214 –216 –218 –220 –222 –224 0 0.5 1.0 1.5 SLEW RATE (V/ns) Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/ REFIN 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 2.3 2.4 2.5 FREQUENCY (GHz) Figure 15. VCO Tuning Voltage vs. Frequency – ...

Page 21

... Figure 21. LVDS Output (Differential) @ 100 MHz 0.4 0.2 0 –0.2 –0 Figure 22. LVDS Output (Differential) @ 800 MHz 2.8 1.8 0.8 –0 2.8 1.8 0.8 –0 Rev Page AD9517 TIME (ns 100 TIME (ns) Figure 23.CMOS Output @ 25 MHz TIME (ns) Figure 24. CMOS Output @ 250 MHz 12 ...

Page 22

... AD9517-1 1600 1400 1200 1000 800 0 1 FREQUENCY (GHz) Figure 25. LVPECL Differential Swing vs. Frequency 700 600 500 0 100 200 300 400 500 FREQUENCY (MHz) Figure 26. LVDS Differential Swing vs. Frequency 100 200 300 OUTPUT FREQUENCY (MHz) Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load – ...

Page 23

... Figure 35. Phase Noise (Additive) LVDS @ 800 MHz, Divide-by-2 –120 –130 –140 –150 –160 –170 10 10M 100M Figure 36. Phase Noise (Additive) CMOS @ 50 MHz, Divide-by-20 Rev Page AD9517-1 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 ...

Page 24

... AD9517-1 –100 –110 –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 37. Phase Noise (Additive) CMOS @ 250 MHz, Divide-by-4 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO @ 2.4576 GHz; PFD = 15.36 MHz; LBW = 55 kHz; LVPECL Output = 122.88 MHz – ...

Page 25

... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9517-1 ...

Page 26

... REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9517-1 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE N DELAY COUNTERS N DIVIDER DIVIDE ...

Page 27

... PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 23. Setting the PFD Polarity Register Function 0x10<7> PFD polarity positive (higher control voltage produces higher frequency) 0x10<7> PFD polarity negative (higher control voltage produces lower frequency) Rev Page AD9517-1 CP ...

Page 28

... REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9517-1 Figure 42. High Frequency Clock Distribution or External VCO >1600 MHz GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER ...

Page 29

... Initiate VCO calibration. 0x232<0> 0x1E0<2:0> VCO divider set to divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6. 0x1E1<0> Use the VCO divider as source for distribution section. 0x1E1<1> VCO selected as the source. Rev Page AD9517-1 CP ...

Page 30

... REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9517-1 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER DIVIDE ...

Page 31

... PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. Table 27. Setting the PFD Polarity Register Function 0x10<7> PFD polarity positive (higher control voltage produces higher frequency) 0x10<7> PFD polarity negative (higher control voltage produces lower frequency) Rev Page AD9517-1 ...

Page 32

... REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9517-1 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER DIVIDE ...

Page 33

... The antibacklash pulse width is set by 0x17<1:0>. An important limit to keep in mind is the maximum frequency allowed into the PFD. The maximum input frequency into the PFD is a function of the antibacklash pulse setting, as specified in the phase/frequency detector section of Table 2. Rev Page AD9517-1 CPRSET VCP LD LOCK DETECT ...

Page 34

... It is possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side ( REFIN ) should be decoupled via a suitable capacitor to a quiet ground. Figure 47 , the PFD frequency, VCO shows the equivalent circuit of REFIN. Rev Page AD9517-1 LF VCO CHARGE PUMP ...

Page 35

... A counter is not used ( and the equation simplifies /R) × (P × VCO REF When the divide is a fixed divide 16, or 32, in which case the previous equation also applies. Rev Page AD9517-1 × N/R REF × N/R REF ...

Page 36

... AD9517-1 By using combinations of DM and FD modes, the AD9517 can achieve values of N all the way down Table 28 shows how a 10 MHz reference input may be locked to any integer multiple of N. Note that the same value of N may be derived in different ways, as illustrated by the case 12. The user may choose a fixed ...

Page 37

... PLL off feedback input for an external VCO/VCXO using the internal PLL when the internal VCO is not used. The CLK/ CLK input can be used for frequencies up to 2.4 GHz. Rev Page AD9517-1 AD9517-1 110µA DLD V LD OUT ...

Page 38

... AD9517-1 Holdover The AD9517 PLL has a holdover function. Holdover is implemented by putting the charge pump into a high impedance state. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. ...

Page 39

... VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 52. The PLL reference monitors have two threshold frequencies: normal and extended (see Table 16). The reference frequency monitor thresholds are selected in 0x1F. Rev Page AD9517-1 ...

Page 40

... AD9517-1 REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 STATUS REFIN (REF1) REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) LF VCO CLK CLK VCO Calibration The AD9517 on-chip VCO must be calibrated to ensure proper operation over process and temperature. The VCO calibration is controlled by a calibration controller running off a divided REFIN clock ...

Page 41

... LVPECL outputs, OUT0 to OUT3. This configuration can pass frequencies up to the maximum frequency of the VCO directly to the LVPECL outputs. The LVPECL outputs may not be able to provide a full voltage swing at the highest frequencies. Rev Page AD9517-1 VCO Divider Used Not used Used ...

Page 42

... AD9517-1 To connect the LVPECL outputs directly to the internal VCO or CLK, the VCO divider must be selected as the source to the distribution section, even if no channel uses it. Either the internal VCO or the CLK can be selected as the source for the direct-to-output routing. Table 31. Settings for Routing VCO Divider Input Directly ...

Page 43

... VCO is connected directly to the output, the duty cycle is 50%. 50% If the CLK input is routed directly to the output, the duty cycle of the output is the same as the CLK input. 50%; requires 50%; requires Rev Page AD9517-1 D Output Duty Cycle DCCOFF = 1 DCCOFF = 0 ...

Page 44

... AD9517-1 Phase Offset or Coarse Time Delay (0, 1) Each channel divider allows for a phase offset coarse time delay programmed by setting register bits (see Table 38). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. This delay is with respect to a nondelayed output (that is, with a phase offset of zero) ...

Page 45

... X.1 Odd ( X.1 X.1 Even (N + 1)/ X Odd X.1 X 1)/ X X.2 X 1)/ X X.2 X.2 Rev Page AD9517 Output X.1 X.2 Duty Cycle X.1 X.1 X Even, Odd Even, Odd Even, Odd Even, Odd (N (N Even, Odd Even, Odd ...

Page 46

... AD9517-1 Table 43. Divider 2 and Divider 3 Duty Cycle; VCO Divider Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider Input Duty Cycle = X.1 X.2 VCO Divider X.1 X.1 X.2 X.2 Even 1 1 Odd = Odd = Even Even X.1 X.1 Odd Even X.1 X.1 Even Odd ...

Page 47

... Rev Page RAMP ⎛ No − ⎜ − × 0.34 1600 I 10 ⎜ RAMP ⎝ AD9517-1 )) × 1.3286 − ⎞ of Caps 1 × ⎟ ⎟ ⎠ RAMP ...

Page 48

... AD9517-1 Synchronization of the outputs is executed in several ways: • The SYNC pin is forced low and then released (manual SYNC). • By setting and then resetting any one of the following three bits: the soft SYNC bit (0x230<0>), the soft reset bit (0x00<5> [mirrored]), or the distribution power-down bit (0x230< ...

Page 49

... If the pins are not connected (unused acceptable to use the total power-down mode. Rev Page CHANNEL DIVIDER OUTPUT CLOCKING selectable from OD 3.3V OUT OUT GND Figure 57. LVPECL Output Simplified Equivalent Circuit AD9517-1 can be S_LVPECL ...

Page 50

... AD9517-1 LVDS/CMOS Outputs: OUT4 to OUT7 OUT4 to OUT7 can be configured as either an LVDS differential output pair of CMOS single-ended outputs. The LVDS outputs allow for selectable output current from ~1. mA. The LVDS output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change ...

Page 51

... Distribution Power-Down section). Individual Circuit Block Power-Down Other AD9517 circuit blocks (such as CLK, REF1, and REF2) can be powered down individually. This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed. Rev Page AD9517-1 ...

Page 52

... CS (chip select bar active low control that gates the read and write cycles. When CS is high, SDO and SDIO are in a high impedance state. This pin is internally pulled kΩ resistor to VS. SCLK 13 AD9517 SERIAL SDO 15 CONTROL ...

Page 53

... Streaming mode always terminates when it hits Address 0x232. Note that unused addresses are not skipped during multibyte I/O operations. Table 48. Streaming Mode (No Addresses Are Skipped) Write Mode LSB first MSB first Rev Page AD9517-1 Address Direction Stop Sequence Increment 0x230, 0x231, 0x232, stop Decrement 0x01, 0x00, 0x232, stop ...

Page 54

... AD9517-1 Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 R A12 = 0 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 62. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data ...

Page 55

... Minimum period that SCLK should Logic High state HI t Minimum period that SCLK should Logic Low state LO t SCLK to valid SDIO and SDO (see Figure 65 CLK BIT N BIT Figure 67. Serial Control Port Timing—Write Rev Page AD9517 ...

Page 56

... AD9517-1 REGISTER MAP OVERVIEW Table 51. Register Map Overview Addr Bit 7 (Hex) Parameter (MSB) Bit 6 Serial Port Configuration 00 Serial Port SDO LSB First Configuration Active Read Back Control PLL 10 PFD and PFD Charge Pump Polarity 11 R Counter 12 Blank 13 A Counter ...

Page 57

... LVDS/CMOS Output Polarity OUT7 LVDS/ OUT7 OUT7 Select CMOS CMOS B LVDS/CMOS Output Polarity Blank Rev Page AD9517-1 Bit 2 Bit 1 Bit 0 (LSB) OUT4 Delay Bypass OUT4 Ramp Current OUT5 Delay Bypass OUT5 Ramp Current OUT6 Delay Bypass OUT6 Ramp Current OUT7 Delay ...

Page 58

... AD9517-1 Addr Bit 7 (Hex) Parameter (MSB) Bit 6 LVPECL Channel Dividers 190 Divider 0 Divider 0 Low Cycles (PECL) 191 Divider 0 Divider 0 Bypass Nosync 192 Blank 193 to 195 196 Divider1 Divider 1 Low Cycles (PECL) 197 Divider 1 Divider 1 Bypass Nosync 198 Blank LVDS/CMOS Channel Dividers ...

Page 59

... Power-Down and Sync 231 Update All Registers 232 Update All Registers Bit 5 Bit 4 Bit 3 Reserved Blank Blank Rev Page AD9517-1 Bit 2 Bit 1 Bit 0 (LSB) Power- Power- Soft Sync Down Sync Down Distribution Reference Reserved Update All Registers (Self-Clearing Bit) ...

Page 60

... AD9517-1 REGISTER MAP DESCRIPTIONS Table 52 through Table 61 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, and <5:2> refers to the range of bits from Bit 5 through Bit 2. ...

Page 61

... A and B counters. <4> I (mA 0.6 1 1.2 0 1.8 1 2.4 0 3.0 1 3.6 0 4.2 1 4.8 Charge Pump Mode High impedance state. Force source current (pump up). Force sink current (pump down). Normal operation. Mode Normal operation. Asynchronous power-down. Normal operation. Synchronous power-down. supply voltage. CP /2. CP Rev Page AD9517-1 ...

Page 62

... AD9517-1 Reg. Addr (Hex) Bit(s) Name Description 16 <4> Reset All Reset R, A, and B counters. Counters <4> normal. <4> reset R, A, and B counters. 16 <3> B Counter B counter bypass. This is valid only when operating the prescaler in FD mode. Bypass <3> normal. <3> counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider ...

Page 63

... Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD) (active low LVL Holdover active (active low LVL LD pin comparator output (active low). Antibacklash Pulse Width (ns) 2.9 1.3 6.0 2.9 PFD Cycles to Determine Lock 255 (default) Rev Page AD9517-1 ...

Page 64

... AD9517-1 Reg. Addr (Hex) Bit(s) Name Description 19 <7:6> <7> <6> Counters 0 0 SYNC Pin 0 1 Reset <5:3> R Path Delay <5:3> R Path Delay (see Table 2). 19 <2:0> N Path Delay <2:0> N Path Delay (see Table 2). 1A <6> Reference Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect Frequency the VCO frequency monitor’ ...

Page 65

... LVL LD pin comparator output (active high LVL VS (PLL supply DYN REF1 clock (differential reference when in differential mode DYN REF2 clock (not available in differential mode DYN Selected reference to PLL (differential reference when in differential mode). Rev Page AD9517-1 ...

Page 66

... AD9517-1 Reg. Addr (Hex) Bit(s) Name Description <4> <3> <2> <1> <7> Disable Disable or enable the switchover deglitch circuit. Switchover <7> enable switchover deglitch circuit. Deglitch <7> disable switchover deglitch circuit. ...

Page 67

... Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency Frequency > set by Register 0x1A<6>. Threshold <1> REF1 frequency is less than threshold frequency. <1> REF1 frequency is greater than threshold frequency. 1F <0> Digital Lock Readback register: digital lock detect. Detect <0> PLL is not locked. <0> PLL is locked. Rev Page AD9517-1 ...

Page 68

... AD9517-1 Table 54. Fine Delay Adjust: OUT4 to OUT7 Reg. Addr (Hex) Bit(s) Name Description A0 <0> OUT4 Delay Bypass or use the delay function. Bypass <0> use delay function. <0> bypass delay function. A1 <5:3> OUT4 Ramp Selects the number of ramp capacitors used by the delay function. The combination of the number of the Capacitors capacitors and the ramp current sets the delay full scale ...

Page 69

... OUT7 Delay Bypass or use the delay function. Bypass <0> use delay function. <0> bypass delay function. 0 200 1 400 0 600 1 800 0 1000 1 1200 0 1400 1 1600 200 1 400 0 600 1 800 0 1000 1 1200 0 1400 1 1600 Rev Page AD9517-1 ...

Page 70

... AD9517-1 Reg. Addr (Hex) Bit(s) Name Description AA <5:3> OUT7 Ramp Selects the number of ramp capacitors used by the delay function. The combination of the number of Capacitors capacitors and the ramp current sets the delay full scale. <5> <4> <3> Number of Capacitors <2:0> OUT7 Ramp Ramp current for the delay function ...

Page 71

... Normal operation. Partial power-down, reference on; use only if there are no external load resistors. Partial power-down, reference on, safe LVPECL power-down. Total power-down, reference off; use only if there are no external load resistors. Rev Page AD9517-1 Output On Off Off Off Output On ...

Page 72

... AD9517-1 Table 56. LVDS/CMOS Outputs Reg. Addr (Hex) Bit(s) Name 140 <7:5> OUT4 Output Polarity 140 <4> OUT4 CMOS B 140 <3> OUT4 Select LVDS/CMOS 140 <2:1> OUT4 LVDS Output Current 140 <0> OUT4 Power-Down 141 <7:5> OUT5 Output Polarity 141 <4> OUT5 CMOS B 141 <3> OUT5 Select LVDS/CMOS 141 <2:1> OUT5 LVDS Output Current Description In CMOS mode, < ...

Page 73

... Inverting In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode. <4> turn off the CMOS B output. <4> turn on the CMOS B output. Select LVDS or CMOS logic levels. <3> LVDS. <3> CMOS. Rev Page AD9517-1 OUT6 (LVDS) Noninverting Noninverting Noninverting Noninverting Inverting Inverting ...

Page 74

... AD9517-1 Reg. Addr (Hex) Bit(s) Name 143 <2:1> OUT7 LVDS Output Current 143 <0> OUT7 Power-Down Table 57. LVPECL Channel Dividers Reg. Addr (Hex) Bit(s) Name 190 <7:4> Divider 0 Low Cycles 190 <3:0> Divider 0 High Cycles 191 <7> Divider 0 Bypass 191 <6> Divider 0 Nosync 191 <5> Divider 0 Force High 191 < ...

Page 75

... Duty-cycle correction function. <0> enable duty-cycle correction. <0> disable duty-cycle correction. Number of clock cycles of divider 3.1 input during which 3.1 output stays low. Number of clock cycles of 3.1 divider input during which 3.1 output stays high. Refer to LVDS/CMOS channel divider function description. Rev Page AD9517-1 ...

Page 76

... AD9517-1 Reg. Addr (Hex) Bit(s) Name 19F <3:0> Phase Offset Divider 3.1 1A0 <7:4> Low Cycles Divider 3.2 1A0 <3:0> High Cycles Divider 3.2 1A1 <5> Bypass Divider 3.2 1A1 <4> Bypass Divider 3.1 1A1 <3> Divider 3 Nosync 1A1 <2> Divider 3 Force High 1A1 <1> Start High Divider 3.2 1A1 <0> Start High Divider 3.1 1A2 <0> Divider 3 DCCOFF Table 59 ...

Page 77

... The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed. That is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. <0> same as SYNC high. <0> same as SYNC low. Rev Page AD9517-1 ...

Page 78

... AD9517-1 APPLICATION NOTES USING THE AD9517 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of its sampling clock. An ADC can be thought sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock ...

Page 79

... The AD9517 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. CMOS Rev Page AD9517-1 VS 100Ω 50Ω 10Ω CMOS CMOS 100Ω ...

Page 80

... ORDERING GUIDE Model Temperature Range 1 AD9517-1BCPZ −40°C to +85°C 1 AD9517-1BCPZ-REEL7 −40°C to +85°C 1 AD9517-1/PCBZ RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 7.00 BSC SQ 0.60 MAX 37 36 TOP 6 ...