AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 7

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Parameter
CMOS CLOCK OUTPUTS
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL
PROPAGATION DELAY, t
OUTPUT SKEW, LVPECL OUTPUTS
LVDS
PROPAGATION DELAY, t
OUTPUT SKEW, LVDS OUTPUTS
CMOS
PROPAGATION DELAY, t
OUTPUT SKEW, CMOS OUTPUTS
DELAY ADJUST
OUT4A, OUT4B, OUT5A, OUT5B, OUT6A,
OUT6B, OUT7A, OUT7B
Output Rise Time, t
Output Fall Time, t
High Frequency Clock Distribution Configuration
Clock Distribution Configuration
Variation with Temperature
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
Shortest Delay Range
Longest Delay Range
All LVDS Outputs Across Multiple Parts
All CMOS Outputs Across Multiple Parts
Output Rise Time, t
Output Fall Time, t
Output Rise Time, t
Output Fall Time, t
For All Divide Values
Variation with Temperature
Output Frequency
Output Voltage High (V
Output Voltage Low (V
For All Divide Values
Variation with Temperature
Zero Scale
Full Scale
Zero Scale
Full Scale
Quarter Scale
3
FP
RP
FL
FC
RL
RC
PECL
LVDS
CMOS
4
4
, CLK-TO-LVPECL OUTPUT
, CLK-TO-LVDS OUTPUT
, CLK-TO-CMOS OUTPUT
OL
OH
)
)
1
1
1
Min
V
S
− 0.1
Min
835
773
1.4
1.6
50
540
200
1.72
5.7
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Typ
Typ
70
70
995
933
0.8
5
13
170
160
1.8
1.25
6
25
495
475
2.1
2.6
4
28
315
880
570
2.31
8.0
Max
180
180
1180
1090
15
40
220
350
350
2.1
62
150
430
1000
985
2.6
66
180
675
680
1180
950
2.89
10.1
Max
250
0.1
Unit
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ns
ps/°C
ps
ps
ps
ps
ps
ns
ps/°C
ps
ps
ps
ps
ps
ps
ns
ns
Unit
MHz
V
V
Test Conditions/Comments
Termination = 50 Ω to V
20% to 80%, measured differentially
80% to 20%, measured differentially
See Figure 42
See Figure 44
Termination = 100 Ω differential; 3.5 mA
20% to 80%, measured differentially
20% to 80%, measured differentially
Delay off on all outputs
Delay off on all outputs
Termination = open
20% to 80%, C
80% to 20%, C
Fine delay off
Fine delay off
LVDS and CMOS
0xA1 (0xA4) (0xA7) (0xAA) <5:0> 101111b
0xA2 (0xA5) (0xA8) (0xAB) <5:0> 000000b
0xA2 (0xA5) (0xA8) (0xAB) <5:0> 101111b
0xA1 (0xA4) (0xA7) (0xAA) <5:0> 000000b
0xA2 (0xA5) (0xA8) (0xAB) <5:0> 000000b
0xA2 (0xA5) (0xA8) (0xAB) <5:0> 001100b
0xA2 (0xA5) (0xA8) (0xAB) <5:0> 101111b
Test Conditions/Comments
Single-ended; termination = 10 pF
See Figure 27
@ 1 mA load
@ 1 mA load
LOAD
LOAD
= 10 pF
= 10 pF
S
− 2 V; level = 810 mV
AD9517-1
2
2