AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 36

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9517-1
By using combinations of DM and FD modes, the AD9517 can
achieve values of N all the way down to N = 1. Table 28 shows
how a 10 MHz reference input may be locked to any integer
multiple of N.
Note that the same value of N may be derived in different ways,
as illustrated by the case of N = 12. The user may choose a fixed
divide mode P = 2 with B = 6, or use the dual modulus mode
2/3 with A = 0, B = 6, or use the dual modulus mode 4/5 with
A = 0, B = 3.
A and B Counters
The AD9517 B counter can be bypassed (B = 1). This B counter
bypass mode is only valid when using the prescaler in FD mode.
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
Unlike the R counter, an A = 0 is actually a zero. The B counter
must be ≥3 or bypassed.
Table 28. How a 10 MHz Reference Input May Be Locked to Any Integer Multiple of N
FREF
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
1
2
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
A
X
X
X
X
X
X
0
1
2
1
X
0
1
X
0
0
1
B
1
1
3
4
5
3
3
3
3
4
5
5
5
6
6
3
3
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N
1
2
3
4
5
6
6
7
8
9
10
10
11
12
12
12
13
FVCO
10
20
30
40
50
60
60
70
80
90
100
100
110
120
120
120
130
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency specified in Table 2.
This is the prescaler input frequency (VCO or CLK) divided by P.
Although manual reset is not normally required, the A/B counters
have their own reset bit. A and B counters can be reset using the
shared reset bit of the R, A, and B counters. They may also be
reset through a SYNC operation.
R, A, and B Counters: SYNC Pin Reset
The R, A and B counters may also be reset simultaneously
through the SYNC pin. This function is controlled by 0x19<7:6>
(see Table 53). The SYNC pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays may be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See 0x19 in Table 53.
Mode
FD
FD
FD
FD
FD
FD
DM
DM
DM
DM
FD
DM
DM
FD
DM
DM
DM
Notes
P = 1, B = 1 (bypassed)
P = 2, B = 1 (bypassed)
P = 1, B = 3
P = 1, B = 4
P = 1, B = 5
P = 2, B = 3
P and P + 1 = 2 and 3, A = 0, B = 3
P and P + 1 = 2 and 3, A = 1, B = 3
P and P + 1 = 2 and 3, A = 2, B = 3
P and P + 1 = 2 and 3, A = 1, B = 4
P = 2, B = 5
P and P + 1 = 2 and 3, A = 0, B = 5
P and P + 1 = 2 and 3, A = 1, B = 5
P = 2, B = 6
P and P + 1 = 2 and 3, A = 0, B = 6
P and P + 1 = 4 and 5, A = 0, B = 3
P and P + 1 = 4 and 5, A = 1, B = 3