AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 51

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

If the AD9517 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section). A VCO
calibration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9517 can be selectively powered
down. There are three PLL operating modes set by 0x10<1:0>,
as shown in Table 53.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency
jumps. The device goes into power-down on the occurrence of
the next charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
0x230<1> = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and can be damaged
under certain termination conditions.
Rev. 0 | Page 51 of 80
Individual Clock Output Power-Down
Any of the clock distribution outputs may be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output
(see Table 51). The LVDS/CMOS outputs may be powered
down, regardless of their output load configuration.
The LVPECL outputs have multiple power-down modes
(see Table 55), which give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
0x230<1> = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Other AD9517 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
AD9517-1