AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 31

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Clock Distribution or External VCO <1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is <1600 MHz, a configuration that bypasses the
VCO divider can be used. This only differs from the High
Frequency Clock Distribution—CLK or External VCO >1600 MHz
section in that the VCO divider (divide-by-2, divide-by-3,
divide-by-4, divide-by-5, and divide-by-6) is bypassed. This
limits the frequency of the clock source to <1600 MHz (due to
the maximum input frequency allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, the register settings shown in Table 25 should be used.
Table 25. Settings for Clock Distribution <1600 MHz
Register
0x10<1:0> = 01b
0x1E1<0> = 1b
0x1E1<1> = 0b
When using the internal PLL with an external VCO <1600 MHz,
the PLL must be turned on.
Function
PLL asynchronous power-down (PLL off )
Bypass the VCO divider as source for
distribution section
CLK selected as the source
Rev. 0 | Page 31 of 80
Table 26. Settings for Using Internal PLL with External VCO
<1600 MHz
Register
0x1E1<0> = 1b
0x10<1:0> = 00b
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 27. Setting the PFD Polarity
Register
0x10<7> = 0
0x10<7> = 1
Function
Bypass the VCO divider as source for
distribution section
PLL normal operation (PLL on) along with
other appropriate PLL settings in 0x10 to 0x1E
Function
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control
voltage produces lower frequency)
AD9517-1