AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 46

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9517-1
Table 43. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd
Even
Odd = 3
Odd = 5
N
1
1
Even
(N
Even
(N
Odd
(M
Odd
(M
Odd
(M
Even
(N
Even
(N
Odd
(M
Odd
(M
Odd
(M
Odd
(M
Odd
(M
1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ M
= M
= M
= N
= N
= N
= M
= M
= N
= N
= N
= N
= N
D
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
)
)
)
)
+ 2
N
1
1
1
1
1
1
1
1
Even
(N
Even
(N
Even
(N
Even
(N
Odd
(M
Odd
(M
Odd
(M
X.2
X.2
X.2
X.2
X.2
X.2
X.2
X.2
+ M
= M
= M
= M
= M
= N
= N
= N
D
X.2
X.2
X.2
X.2
X.2
X.2
X.2
X.2
X.2
+ 1)
+ 1)
+ 1)
)
)
)
)
+ 2
Output
Duty Cycle
50%
(1 + X%)/3
(2 + X%)/5
50%
50%
50%
(3N
(6N
(5N
(10N
50%
50%
50%
50%
50%
(6N
9N
(3(2N
(2N
(10N
15N
(5(2 N
(2 N
X.2
X.1
X.1
X.1
X.1
X.2
X.2
X.2
X.1
X.1
+ 13 + X%)/
N
X.1
+ 4 + X%)/
+ 9)
+ 7 + X%)/
+ 3))
X.1
N
+ 22 + X%)/
+ 3))
X.2
+ 15)
+ 3)
X.2
+ 3)
+ 9N
+ 15N
X.1
X.1
Rev. 0 | Page 46 of 80
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Table 44. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction On (DCCOFF = 0)
Input
Clock
Duty
Cycle
50%
50%
X%
X%
50%
X%
50%
X%
50%
X%
50%
X%
Phase Offset or Coarse Time Delay (Divider 2 and Divider 3)
Divider 2 and Divider 3 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Table 45).
Table 45. Setting Phase Offset and Division for Divider 2 and
Divider 3
Divider
2
3
Let:
Δ
Φ
1 × PO<0>.
T
T
t
X.1
X.2
x.y
= delay (in seconds).
= 16 × SH<0> + 8 × PO<3> + 4 × PO<2> + 2 × PO<1> +
= period of the clock signal at the input to D
= period of the clock signal at the input to D
2.1
2.2
3.1
3.2
N
1
Even
(N
1
Even
(N
Odd
(M
Odd
(M
Even
(N
Even
(N
Odd
(M
Odd
(M
Odd
(M
Odd
(M
X.1
Start
High (SH)
0x19C<0>
0x19C<1>
0x1A1<0>
0x1A1<1>
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ M
= M
= M
= N
= N
= M
= M
= N
= N
= N
= N
D
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
)
)
)
)
+ 2
Phase
Offset (PO)
0x19A<3:0>
0x19A<7:4>
0x19F<3:0>
0x19F<7:4>
N
1
1
1
1
1
1
Even
(N
Even
(N
Even
(N
Even
(N
Odd
(M
Odd
(M
X.2
X.2
X.2
X.2
X.2
X.2
X.2
+ M
= M
= M
= M
= M
= N
= N
D
X.2
X.2
X.2
X.2
X.2
X.2
X.2
X.2
+ 1)
+ 1)
)
)
)
)
+ 2
Low
Cycles M
0x199<7:4>
0x19B<7:4>
0x19E<7:4>
0x1A0<7:4>
Output
Duty Cycle
50%
50%
X% (High)
50%
50%
(N
(2N
50%
50%
50%
50%
50%
(2N
3N
((2N
X.1
X.2
X.1
X.1
X.1
+ 1 + X%)/
X.1
X.2
+ 4 + X%)/
N
+ 3)
+ 3)(2N
X.2
(in seconds).
(in seconds).
High
Cycles N
0x199<3:0>
0x19B<3:0>
0x19E<3:0>
0x1A0<3:0>
+ 3N
X.2
X.1
+ 3))
+