AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 50

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9517-1
LVDS/CMOS Outputs: OUT4 to OUT7
OUT4 to OUT7 can be configured as either an LVDS
differential output or as a pair of CMOS single-ended outputs.
The LVDS outputs allow for selectable output current from
~1.75 mA to ~7 mA.
The LVDS output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVDS output can be powered down
if not needed to save power.
OUT4 to OUT7 can also be CMOS outputs. Each LVDS output
can be configured to be two CMOS outputs. This provides for
up to eight CMOS outputs: OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, and OUT7B. When an output is
configured as CMOS, the CMOS Output A is automatically
turned on. The CMOS Output B can be turned on or off
independently. The relative polarity of the CMOS outputs can also
be selected for any combination of inverting and noninverting. See
Table 56, 0x140<7:5>, 0x141<7:5>, 0x142<7:5>, and 0x143<7:5>.
Each LVDS/CMOS output can be powered-down as needed to
save power. The CMOS output power-down is controlled by the
same bit that controls the LVDS power-down for that output.
This power-down control affects both the CMOS A and
CMOS B outputs. However, when the CMOS A output is powered
up, the CMOS B output can be powered on or off separately.
RESET MODES
The AD9517 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Figure 58. LVDS Output Simplified Equivalent Circuit with
Figure 59. CMOS Equivalent Output Circuit
3.5 mA Typical Current Source
3.5mA
3.5mA
V
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OUT
OUT
OUT
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Power-On Reset—Start-Up Conditions When V
Applied
A power-on reset (POR) is issued when the V
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Table 51. At
power-on, the AD9517 also executes a SYNC operation, which
brings the outputs into phase alignment according to the default
settings.
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default
settings.
Soft Reset via 0x00<5>
A soft reset is executed by writing 0x00<5> and 0x00<2> = 1b.
This bit is not self-clearing; therefore, it must be cleared by
writing 0x00<5> and 0x00<2> = 0b to reset it and complete the
soft reset operation. A soft reset restores the default values to
the internal registers. The soft reset bit does not require an
update registers command (0x232) to be issued.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9517 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9517. The chip remains in
this power-down state until PD is brought back to Logic High.
When woken up, the AD9517 returns to the settings programmed
into its registers prior to the power-down, unless the registers
are changed by new programming while the PD pin is held low.
The PD power-down shuts down the currents on the chip,
except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9517 is in a PD power-down, the chip is in the
following state:
•
•
•
•
•
•
•
The PLL is off (asynchronous power-down).
The VCO is off.
The CLK input buffer is off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
S
power supply is
S
Is