mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 182

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Analog-to-Digital Converter (S08ADC12V1)
are too fast, the clock must be divided to the appropriate frequency. This divider is specified by the ADIV
bits and can be divide-by 1, 2, 4, or 8.
9.4.2
The pin control registers (APCTL3, APCTL2, and APCTL1) disable the I/O port control of the pins used
as analog inputs.When a pin control register bit is set, the following conditions are forced for the associated
MCU pin:
9.4.3
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled
when the ADTRG bit is set. This source is not available on all MCUs. Consult the module introduction for
information on the ADHWT source specific to this MCU.
When ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion is initiated
on the rising edge of ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is
ignored. In continuous convert configuration, only the initial rising edge to launch continuous conversions
is observed. The hardware trigger function operates in conjunction with any of the conversion modes and
configurations.
9.4.4
Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE
bits. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be
configured for low power operation, long sample time, continuous conversion, and automatic compare of
the conversion result to a software determined compare value.
9.4.4.1
A conversion is initiated:
If continuous conversions are enabled, a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.
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The output buffer is forced to its high impedance state.
The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
The pullup is disabled.
Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is
selected.
Following a hardware trigger (ADHWT) event if hardware triggered operation is selected.
Following the transfer of the result to the data registers when continuous conversion is enabled.
Input Select and Pin Control
Hardware Trigger
Conversion Control
Initiating Conversions
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor