mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 385

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

16.5
This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.
16.5.1
The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference will stabilize in t
reference is stable, the FLL will acquire lock in t
16.5.1.1
Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched
to upon reset are FEE, FBE, and FBI modes (see
first configuring the MCG for one of these three initial modes. Care must be taken to check relevant status
bits in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
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1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. If the RANGE bit (bit 5) in MCGC2 is set, set DIV32 in MCGC3 to allow access to the proper
3. Write to MCGC1 to select the clock mode.
4. Once the proper configuration bits have been set, wait for the affected bits in the MCGSC register
RDIV values.
— If entering FEE mode, set RDIV appropriately, clear the IREFS bit to switch to the external
— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS
— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
to be changed appropriately, reflecting that the MCG has moved into the proper mode.
— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and
Initialization / Application Information
reference, and leave the CLKS bits at %00 so that the output of the FLL is selected as the
system clock source.
bits to %10 so that the external reference clock is selected as the system clock source. The
RDIV bits should also be set appropriately here according to the external reference frequency
because although the FLL is bypassed, it is still on in FBE mode.
useful if the application will switch back and forth between internal and external modes. For
minimum power consumption, leave the internal reference disabled while in an external clock
mode.
EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the
MCG Module Initialization Sequence
Initializing the MCG
If the internal reference is not already trimmed, the BDIV value should not
be changed to divide-by-1 without first trimming the internal reference.
Failure to do so could result in the MCU running out of specification.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
irefst
microseconds before the FLL can acquire lock. As soon as the internal
fll_acquire
NOTE
Figure
16-9). Reaching any of the other modes requires
milliseconds.
Multipurpose Clock Generator (MCGV3)
16-17