mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 40

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Modes of Operation
The V1 ColdFire core does not differentiate between stop and wait modes. The difference between the two
is at the device level. In stop mode, most peripheral clocks are shut down; in wait mode, they continue to
run.
The ENBDM bit in the XCSR register must be set prior to entering wait mode if the device is required to
respond to BDM commands once in wait mode.
The low voltage detector, if enabled, can be configured to interrupt the CPU and exit wait mode into run
mode.
When an interrupt request occurs, the CPU exits wait mode and resumes processing, beginning with the
stacking operations leading to the interrupt service routine.
3.7
One of three stop modes are entered upon execution of a STOP instruction when SOPT[STOPE] is set.
SOPT[WAITE] must be clear. In stop3 mode, the bus and CPU clocks are halted. If the ENBDM bit is set
prior to entering stop4, only the peripheral clocks are halted. The MCG module can be configured to leave
the reference clocks running. See
information.
The stop modes are selected by setting the appropriate bits in the SPMSC2 register.
the control bits that affect mode selection under various conditions. The selected mode is entered following
the execution of a STOP instruction.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in stop or wait mode. The
BACKGROUND command can be used to wake the MCU from stop4 and enter halt mode if the ENBDM
bit was set prior to entering stop mode. After entering halt mode, all background commands are available.
3.7.1
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in
of the internal circuitry of the MCU is powered off in stop2 mode, with the exception of the RAM. Upon
entering stop2 mode, all I/O pin control signals are latched so that the pins retain their states during stop2
mode. Exiting from stop2 mode is performed by asserting either wakeup pin: RESET or IRQ.
3-4
Stop Modes
Stop2 Mode
If neither the WAITE or STOPE bit is set when the CPU executes a STOP
instruction, the MCU does not enter stop modes. It initiates an illegal
opcode reset (if CPUCR[IRD]=0) or generates an illegal instruction
exception (otherwise), if enabled.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Chapter 16, “Multipurpose Clock Generator
NOTE
(MCGV3),” for more
Table 3-1
Freescale Semiconductor
Table
shows all of
3-1. Most