tda8031hl-c107 NXP Semiconductors, tda8031hl-c107 Datasheet - Page 21

• Manufacturer Part Number: tda8031hl-c107
• Description: Usb Smart Card Reader Otp Or Rom
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.1.4.5
The UART Status Register (USR) is used by the microcontroller to monitor the activity of the ISO UART and of the
time-out counter.
Table 15 UART status register (address 0EH; read only); note 1
Note
1. All bits are cleared after reset.
Table 16 Description of the USR bits
2003 Jul 04
USB smart card reader (OTP or ROM)
TO3
BIT
7
7
6
5
4
3
2
1
0
UART status register
SYMBOL
TBE/RBF
OVR
FER
TO3
TO1
EA
PE
6
Time-Out counter 3: Bit TO3 = 1 when counter 3, or counters 3 + 2 or counters
3 + 2 + 1 have reached their terminal count.
not used
Time-Out counter 1: Bit TO1 = 1 when counter 1 has reached its terminal count.
Early Answer: When bit RST is LOW, EA is HIGH if the first start bit on the I/O during
ATR has been detected between 200 and 384 clock pulses (all activities on the I/O
during the first 200 clock pulses with RST LOW are not taken into account). When RST
is HIGH, EA is HIGH if a start bit has been detected before the 384th clock pulse. These
two features are reinitialized at each toggling of RST.
Parity Error: In T = 0 protocol, PE = 1 if the UART has detected a number of received
characters with parity error equal to the number written in PEC2, PEC1 and PEC0 or if a
transmitted character has been NAKed by the card a number of times equal to the value
programmed in PEC2, 1 and 0. It is set at 10.5 ETU in reception mode and at 11.5 ETU
in transmission mode.
In T = 0 protocol, a character received with a parity error is not stored in the FIFO, the
card is supposed to repeat this character. In T = 1 protocol, a character with a parity
error is stored in the FIFO and the parity error counter is not operating.
Overrun: Bit OVR = 1 if the UART has received a new character while the URR was full.
In this case, at least one character has been lost. OVR is set at 10.5 ETU.
Framing Error: Bit FER = 1 when the I/O was not in high-impedance state at 10.25 ETU
after a start bit. It is reset when the USR has been read-out.
Transmission Buffer Empty/Reception Buffer Full: Bits TBE and RBF share the same bit
within the USR. When in transmission mode the relevant bit is TBE; when in reception
mode it is RBF.
Bit TBE = 1 when the UART is in transmission mode and when the microcontroller may
write the next character to transmit in the UTR. It is reset when the microcontroller has
written data in the Transmit Register, or when the bit T/R within UCR1 has been reset
either automatically or by software. TBE is set at 11.5 ETU in T = 0 protocol and at
10.5 ETU in T = 1 protocol.
Bit RBF = 1 when the FIFO is full. The microcontroller may read some of the characters
in the URR, which clears the bit RBF. Bit RBF is also reset when entering the reception
mode and is set at 10.5 ETU.
TO1
5
EA
4
21
PE
3
DESCRIPTION
OVR
2
TDA8030; TDA8031
FER
1
Product specification
TBE/RBF
0