pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 155

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pnx1700

Manufacturer Part Number
pnx1700
Description
Connected Media Processor
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
Volume 1 of 1
Table 1: PNX17xx Series Module and Bus Clocks
PNX17XX_SER_1
Preliminary data sheet
Bus or
Module
DDR
SDRAM
TM5250
CPU
MMIO
2DDE
PCI
Signal Name
clk_mem
clk_tm
clk_dtl_mmio
clk_2ddE
clk_pci
2.1 The Modules and their Clocks
Description
MM_CLK
The TM5250 clock
MMIO clock
or
DCS clock
2D drawing engine
clock
PCI_SYS_CLK
Remark: Not all the clocks to the modules are generated in the Clock Module, there
will be other clocks which will come into PNX17xx Series from external sources. Some
of these clocks will be fed through the Clock Module so that they may undergo the
same controls required during reset, powerdown, DFT and DfD.
Table 1
The table is organized with the module name, the corresponding internal clock signal
name, a brief description, the operating frequency range or the available clock
speeds, the MMIO registers that control the clock selection and the “standard” clock
used. The “standard” clock used is the recommended clock use when all the clock
generation capabilities are used. This is based on common board systems, however
it is possible to use other clock sources. See
registers layout.
clocking capabilities.
presents a summary of all the clocks used in the PNX17xx Series system.
Table 1
Frequencies
up to 200 MHz
up to 500 MHz
depending on
speed grade
32 MHz
Rev. 1 — 17 March 2006
• 157 MHz
• 144 MHz
• 133 MHz
• 123 MHz
• 115 MHz
• 108 MHz
• 102 MHz
• 54 MHz
• 144 MHz
• 123 MHz
• 108 MHz
• 96 MHz
• 86 MHz
• 78 MHz
• 72 MHz
• 66 MHz
can be used as a quick reference to see the PNX17xx Series
MMIO Clock Module Control
Register(s)
PLL2_CTL
CLK_MEM_CTL
PLL0_CTL
DDS0_CTL
CLK_TM_CTL
CLK_DTL_MMIO_CTL
CLK_2DDE_CTL
CLK_PCI_CTL
The PCI module gets its
primary clock directly from the
PCI_CLK pin.
Section 3. on page 5-32
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Standard
Clock Source
PLL2
PLL0, fed by the input
27 MHz crystal)
1.728 GHz DIVIDERS
1.728 GHz DIVIDERS
N/A
for MMIO
5-4

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