pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 189

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX17XX_SER_1
Preliminary data sheet
Bit
2
1
0
Offset 0x04,7038-0x04,70FCReserved
Module Clocks
Offset 0x04,7100
31:6
5
4
3
2:1
0
Offset 0x04,7104
31:4
Symbol
pd_115
pd_108
pd_102
Reserved
turn_off_ack
tm_stretch_n
sel_pwrdwn_clk_mmio
sel_clk_tm
en_clk_tm
Reserved
CLK_TM_CTL
CLK_MEM_CTL
Acces
s
R/W
R/W
R/W
R/W
R
R/W
W
R/W
R/W
R/W
…Continued
Value
0
0
0
-
0
0
0
0
1
-
Rev. 1 — 17 March 2006
Description
Power down 115 MHz divider in the CAB block.
Power down 108 MHz divider in the CAB block.
Power down 102 MHz divider in the CAB block. Must be set to ‘1’
then ‘0’ before using clk_157 or its derivatives.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
0 - turns on the 75/25 duty cycle adjust circuit
1 - turns off the 75/25 duty cycle adjust circuit
MUST BE SET TO ‘1’ for normal operation.
This bit allows the TM5250 to turn off the MMIO clock
simultaneously with the TM5250 clock. This mechanism allows to
go into deep sleep mode and allows to keep the capability to wake-
up from this deep sleep mode
When deep sleep mode is requested by TM5250, it must turn off its
own clock, clk_tm, by setting en_clk_tm to ‘0’ and
sel_pwrdwn_clk_mmio to ‘1’. Writing to a ‘0’ to en_clk_tm without
setting sel_pwrdwn_clk_mmio to ‘1’ shuts down TM5250 clock
forever (unless a host writes back a ‘1’ to ‘en_clk_tm’ or a system
reset occurs).
Therefore, the ONLY use of sel_pwrdwn_clk_mmio is to set it to ‘1’
at the same time en_clk_tm is set to ‘0’. The TM5250 must run a
waiting loop of 10 27 MHz cycles after the write to CLK_TM_CTL is
done since the clk_tm is not immediately turned off.
Upon wake-up, en_clk_tm and sel_pwrdwn_clk_mmio get their
initial reset value and TM5250 resumes from where it stopped.
Maximum power saving is achieved by turning off the PLL0 and
therefore switch to the 27 MHz xtal_clk clock before requesting a
deep sleep mode. Similarly the other clocks of the system must be
turned off separately if maximum power saving needs to be
achieved. This may include the DDR clock.
Upon wake-up, if a PLL has been turned off, a minimum of 100 s is
required to lock it.
00: clk_tm = 27 MHz xtal_clk
01: clk_tm = tm_stretch_n (output of the duty cycle stretcher)
10: clk_tm = UNDEF
11: clk_tm = AI_WS
1: enable clk_tm
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
(Section 2.8.1 on page
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-17).
5-38