pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 712

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
5.4.3 Tx(Rt) DMA Manager Reads Tx(Rt) Descriptor Arrays
5.4.4 Tx(Rt) DMA manager transmits data
If transmitting other than the last fragment of a multi-fragment packet, the Last bit in
the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To
trigger an interrupt when the packet has been transmitted and transmission status
has been committed to memory, set the Interrupt bit in the descriptor Control field to
1. To have the hardware add a CRC in the frame sequence control field of this
Ethernet frame, set the CRC bit in the descriptor. This should be done if the CRC has
not already been added by software. To enable automatic padding of small packets to
the minimum required packet size, set the Pad bit in the Control field of the descriptor
to 1. In typical applications bits CRC and Pad are both set to 1.
The device driver can set up interrupts using the IntEnable register to wait for a
completion signal from the hardware, or it can periodically inspect (poll) the progress
of transmission. It can also add new packets at the end of the descriptor FIFO, while
hardware consumes descriptors at the start of the FIFO.
The device driver can stop the transmit process by resetting Command.TxEnable and
Command.TxRTEnable to 0. The transmission will not stop immediately; packets
already being transmitted will be transmitted completely and the status will be
committed to memory before deactivating the datapath. The status of the Transmit
Datapath can be monitored by the device driver reading the TxRtStatus/TxStatus bits
in the Status register.
As soon as the (non-) real-time Transmit Datapath is enabled and the corresponding
Tx(Rt)ConsumeIndex and Tx(Rt)ProduceIndex are not equal (i.e. the hardware still
must process packets from the descriptor FIFO), the Tx(Rt)Status bit in the Status
register will return to 1 (active).
When the TxEnable bit (TxRtEnable bit for real-time traffic) is set, the Tx DMA
manager reads the descriptors from memory using block transfers at the address
determined by TxDescriptor and TxConsumeIndex, or, for real-time traffic, at the
address determined by TxRtDescriptor and TxRtConsumeIndex. The block size of
the block transfer is determined by the total number of descriptors owned by the
hardware, which equals Tx(Rt)ProduceIndex – Tx(Rt)ConsumeIndex.
After reading the descriptor, the transmit DMA engine reads the associated packet
data from memory and transmits the packet. After the transfer is complete, the Tx
DMA manager writes status information back to the StatusInfo and StatusTimeStamp
words of the status. The value of the Tx(Rt)ConsumeIndex is only updated after
status information has been committed to memory. The Tx DMA manager continues
to transmit packets until the descriptor FIFO is empty. If the transmit FIFO is empty,
the Tx(Rt)Status bit in the Status register will return to 0 (inactive). If the descriptor
FIFO is empty, the Ethernet hardware will set the Tx(Rt)FinishedInt bit of the
IntStatus register. The Transmit Datapath will still be enabled.
The Tx DMA manager inspects the Last bit of the descriptor Control field when
loading the descriptor. If the Last bit is 0, this indicates that the packet consists of
multiple fragments. The Tx DMA manager gathers all the fragments from the host
memory visiting a string of packet descriptors. It appends the fragments, and sends
Rev. 1 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
23-39