mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 102

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.13.5 Multiple Exceptions
4.13.6 RTI Instruction
4.14 Development Support
4.14.1 Deterministic Opcode Tracking
4-40
MOTOROLA
Each exception has a hardware priority based upon its relative importance to system
operation. Asynchronous exceptions have higher priorities than synchronous
exceptions. Exception processing for multiple exceptions is completed by priority, from
highest to lowest. Priority governs the order in which exception processing occurs, not
the order in which exception handlers are executed.
Unless a bus error, a breakpoint, or a reset occurs during exception processing, the
first instruction of all exception handler routines is guaranteed to execute before
another exception is processed. Because interrupt exceptions have higher priority
than synchronous exceptions, the first instruction in an interrupt handler are executed
before other interrupts are sensed.
Bus error, breakpoint, and reset exceptions that occur during exception processing of
a previous exception are processed before the first instruction of that exception’s
handler routine. The converse is not true. If an interrupt occurs during bus error excep-
tion processing, for example, the first instruction of the exception handler is executed
before interrupts are sensed. This permits the exception handler to mask interrupts
during execution.
Refer to SECTION 5 SINGLE-CHIP INTEGRATION MODULE 2 for detailed
information concerning interrupts and system reset. Refer to the CPU16 Reference
Manual (CPU16RM/AD) for information concerning processing of specific exceptions.
The return-from-interrupt instruction (RTI) must be the last instruction in all exception
handlers except the RESET handler. RTI pulls the exception stack frame that was
pushed onto the system stack during exception processing, and restores processor
state. Normal program flow resumes at the address of the instruction that follows the
last instruction executed before exception processing began.
RTI is not used in the RESET handler because RESET initializes the stack pointer and
does not create a stack frame.
The CPU16 incorporates powerful tools for tracking program execution and for system
debugging. These tools are deterministic opcode tracking, breakpoint exceptions, and
background debug mode. Judicious use of CPU16 capabilities permits in-circuit emu-
lation and system debugging using a bus state analyzer, a simple serial interface, and
a terminal.
The CPU16 has two multiplexed outputs, IPIPE0 and IPIPE1, that enable external
hardware to monitor the instruction pipeline during normal program execution. The
signals IPIPE0 and IPIPE1 can be demultiplexed into six pipeline state signals that
allow a state analyzer to synchronize with instruction stream activity.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC68HC16Y3/916Y3
USER’S MANUAL