mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 104

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.14.3 Opcode Tracking and Breakpoints
4.14.4 Background Debug Mode
4.14.5 Enabling BDM
4.14.5.1 BDM Sources
4-42
MOTOROLA
Breakpoints on instructions that are flushed from the pipeline before execution are not
acknowledged. Operand breakpoints are always acknowledged. There is no break-
point acknowledge bus cycle when BDM is entered. Refer to 5.6.4.1 Breakpoint Ac-
knowledge Cycle for more information about breakpoints.
Breakpoints are acknowledged after a tagged instruction has executed, that is when
the instruction is copied from pipeline stage B to stage C. Stage C contains the opcode
of the previous instruction when execution of the current instruction begins.
When an instruction is tagged, IPIPE0/IPIPE1 reflect the start of execution and the ap-
propriate number of pipeline advances and operand fetches before the breakpoint is
acknowledged. If background debug mode is enabled, these signals model the pipe-
line before BDM is entered.
Microprocessor debugging programs are generally implemented in external software.
CPU16 BDM provides a debugger implemented in CPU microcode. BDM incorporates
a full set of debug options. Registers can be viewed and altered, memory can be read
or written, and test features can be invoked. BDM is an alternate CPU16 operating
mode. While the CPU16 is in BDM, normal instruction execution is suspended, and
special microcode performs debugging functions under external control. While in
BDM, the CPU16 ceases to fetch instructions through the data bus and communicates
with the development system through a dedicated serial interface.
The CPU16 samples the BKPT input during reset to determine whether to enable
BDM. When BKPT is asserted at the rising edge of the RESET signal, BDM operation
is enabled. BDM remains enabled until the next system reset. If BKPT is at logic level
one on the trailing edge of RESET, BDM is disabled. BKPT is relatched on each rising
transition of RESET. BKPT is synchronized internally and must be asserted for at least
two clock cycles before negation of RESET.
When BDM is enabled, external breakpoint hardware and the BGND instruction can
cause the CPU16 to enter BDM. If BDM is not enabled when a breakpoint occurs, a
breakpoint exception is processed.
• If BKPT assertion is synchronized with an operand fetch, breakpoint processing
occurs at the end of the instruction during which BKPT is latched.
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MC68HC16Y3/916Y3
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