mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 465

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

D.10.1 TPU2 Module Configuration Register
TPUMCR — TPU2 Module Configuration Register
STOP — Low-Power Stop Mode Enable
TCR1P[1:0] — Timer Count Register 1 Prescaler Control
TCR2P[1:0] — Timer Count Register 2 Prescaler Control
MC68HC16Y3/916Y3
USER’S MANUAL
STOP
15
0
RESET:
TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal
TPU system clock divided by 2, 4, or 32, depending on the value of the PSCK bit and
the DIV2 bit. If the DIV2 bit is one, the TCR1 counter increments at a rate of the internal
clock divided by two. If DIV2 is zero, TCR1 increment rate is defined by the values in
Table D-55.The prescaler divides this input by 1, 2, 4, or 8. Channels using TCR1
have the capability to resolve down to the TPU system clock divided by four.
TCR2 is clocked from the output of a prescaler. If T2CG = 0, the input to the TCR2
prescaler is the external TCR2 clock source. If T2CG = 1, the input is the TPU system
clock divided by eight. The TCR2P field specifies the value of the prescaler: 1, 2, 4, or
8. Channels using TCR2 have the capability to resolve down to the TPU system clock
divided by eight. Table D-56 is a summary of prescaler output.
0 = Enable TPU2 clocks.
1 = Disable TPU2 clocks.
14
TCR1P[1:0]
0
$YFFFB0 – $YFFFBE
$YFFFC0 – $YFFFCE
$YFFFD0 – $YFFFDE
$YFFFE0 – $YFFFEE
NOTES:
$YFFFF0 – $YFFFFE
1. Y = M111, where M represents the logic state of the module mapping (MM) bit in the
13
0
SCIMCR.
Address
12
TCR2P[1:0]
0
1
Table D-55 TCR1 Prescaler Control Bits
Freescale Semiconductor, Inc.
TCR1P[1:0]
11
0
For More Information On This Product,
Table D-54 TPU2 Register Map
00
01
10
11
EMU
15
10
0
Go to: www.freescale.com
T2CG
9
0
Divide By
Prescaler
STF
1
2
4
8
8
0
Channel 11 Parameter Registers
Channel 12 Parameter Registers
Channel 13 Parameter Registers
Channel 14 Parameter Registers
Channel 15 Parameter Registers
SUPV
7
1
PSCK = 0
f
f
f
f
sys
sys
sys
sys
TCR1 Clock Input
PSCK
128
256
6
0
32
64
TPU2
5
1
PSCK = 1
f
f
f
f
sys
sys
sys
sys
T2CSL
16
32
4
0
4
8
3
0
2
0
IARB[3:0]
$YFFE00
MOTOROLA
0
1
0
D-87
0
0