mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 297

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

13.7 Prescaler
MC68HC16Y3/916Y3
USER’S MANUAL
Capture/compare and PWM units have independent 16-bit free-running counters as a
main timing component. These counters derive their clocks from the prescaler or from
the PCLK input. Figure 13-2 is a prescaler block diagram.
In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler
outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are pro-
vided. Connected to these outputs are two multiplexers, one for the capture/compare
unit, the other for the PWM unit.
Multiplexers can each select one of seven prescaler taps or an external input from the
PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0]
in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter
(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC). After re-
set, the GPT is configured to use system clock divided by four for TCNT and system
clock divided by two for PWMCNT. Initialization software can change the division fac-
tor. The PPR bits can be written at any time, but the CPR bits can only be written once
after reset, unless the GPT is in test or freeze mode.
The prescaler can be read at any time. In freeze mode the prescaler can also be writ-
ten. Word accesses must be used to ensure coherency. If coherency is not needed
byte accesses can be used. The prescaler value is contained in bits [8:0] while bits
[15:9] are unimplemented and are read as zeros.
Freescale Semiconductor, Inc.
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MOTOROLA
13-9