mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 149

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.7.3 Operating Configuration Out of Reset
MC68HC16Y3/916Y3
USER’S MANUAL
All resets are gated by CLKOUT. Asynchronous resets are assumed to be catastroph-
ic. An asynchronous reset can occur on any clock edge. Synchronous resets are timed
to occur at the end of bus cycles. The SCIM2 bus monitor is automatically enabled for
synchronous resets. When a bus cycle does not terminate normally, the bus monitor
terminates it. Table 5-14 is a summary of reset sources.
Internal single byte or aligned word writes are guaranteed valid for synchronous re-
sets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in Figure 5-17.
The logic states of certain pins during reset determine SCIM2 operating configuration.
During reset, the SCIM2 reads pin configuration from DATA[11:2] and DATA0, internal
module configuration from DATA[15:12], and basic operating information from BERR,
MODCLK, DATA1, and BKPT. These pins are normally pulled high internally during
reset, causing the MCU to default to a specific configuration. However, the user can
drive the desired pins low during reset to achieve alternate configurations.
Basic operating options include system clock selection, background mode disable/
enable, and external bus configuration. The SCIM2 supports three external bus
configurations:
Table 5-15 shows the basic configuration options.
Software watchdog
• EXTRST (external reset) drives the external reset pin.
• CLKRST (clock reset) resets the clock module.
• MSTRST (master reset) goes to all other internal circuits.
• Fully-expanded operation with a 24-bit address bus and 16-bit data bus with chip
• Single-chip operation with no external address and data bus
• Partially-expanded operation with a 24-bit address bus and an 8-bit external data
Loss of clock
selects
bus
Power up
External
HALT
Type
Test
External
Source
Monitor
Monitor
Clock
Test
Freescale Semiconductor, Inc.
EBI
For More Information On This Product,
Table 5-14 Reset Source Summary
Timing
Asynch
Asynch
Asynch
Synch
Synch
Synch
Go to: www.freescale.com
Internal HALT assertion
(e.g. double bus fault)
Loss of reference
RESET pin
Test mode
Time out
Cause
V
DD
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
Reset Lines Asserted by
Controller
CLKRST
CLKRST
CLKRST
CLKRST
CLKRST
—
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
MOTOROLA
5-41