mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 347

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC16Y3/916Y3
USER’S MANUAL
Num
E10
E11
E12
E13
E14
E15
E16
NOTES:
E1
E2
E3
E4
E5
E6
E7
E8
E9
Figure A-14 Background Debug Mode Timing Diagram (Freeze Assertion)
1. All AC timing is shown with respect to V
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
4. Chip select access time = t
IPIPE1/DSI
CLKOUT
FREEZE
ECLK Low to Address Valid
ECLK Low to Address Hold
ECLK Low to CS Valid (CS Delay)
ECLK Low to CS Hold
CS Negated Width
Read Data Setup Time
Read Data Hold Time
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
CS Negated to Data High Impedance
ECLK Low to Data Valid (Write)
ECLK Low to Data Hold (Write)
CS Negated to Data Hold (Write)
Address Access Time (Read)
Chip-Select Access Time (Read)
Address Setup Time
(V
DD
and V
Freescale Semiconductor, Inc.
Ecyc
For More Information On This Product,
Characteristic
Ecyc
DDSYN
– t
2
Table A-8 ECLK Bus Timing
B7
EAD
B6
3
– t
ECSD
4
= 5.0 Vdc
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– t
EDSR
– t
IH
B10
/V
EDSR
.
IL
levels unless otherwise noted.
.
5%, V
SS
= 0 Vdc, T
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
A
EDDW
EDHW
ECHW
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
ECDH
EACC
EDHZ
ECDZ
EACS
t
EAD
EAH
EAS
= T
B6
B8
L
to T
H
Min
386
296
10
15
30
30
15
)
0
5
0
1
B11
Max
150
1/2
60
60
1
2
MOTOROLA
16 BDM FRZ TIM
Unit
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
A-21

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