peb2035 ETC-unknow, peb2035 Datasheet - Page 109

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Clear Channel Register Bank (WRITE)
Only accessible if CPY.SW = 1 and CPY.BSEL = 0
Value after RESET: 00
CCB1
CCB2
CCB3
CH1 ... CH24 ... Channel Selection bits
Additional Control Register (WRITE)
Only accessible if CPY.SW = 1 and CPY.BSEL = 0
Value after RESET: 70
ACR
(*)
EXMF ... External Multiframe Synchronization
SLM ... Slip Limit
DLC ... Enable DL Clock
Semiconductor Group
0 ... Normal operation. Bit robbing information and Zero Code Suppression (ZCS, B7 stuffing)
1 ... Clear channel mode. Contents of selected speech/data channel will not be overwritten by bit
0 ... 126 UI peak-to-peak
1 ... 142 UI peak-to-peak
may change contents of the selected speech/data channel if assigned modes are enabled
via bits MODE.SIGM and MODE.CODE.
robbing and ZCS information. Transmission of channel assigned signaling and control of
pulse density is applied by the user.
These bits are reserved for future extensions. When programming register ACR they
have to be set to ‘0’ for correct operation.
Note: Read back value for the high nibble: ’7’
If set, the transmitter of the ACFA can be synchronized externally for multiframe begin via
port XCHPY/AFT (bit EXMF has higher priority than bit DLC). Refer to description of port
XCHPY/AFT for detailed information.
In channel translation mode 0 the maximum permissible wander amplitude can be selected:
If set, ports RCHPY/AFR and XCHPY/AFT provide signals which mark the DL-bit position
within the data stream at RDO and XDI. For XCHPY/AFT, bit EXMF has higher priority than
bit DLC.
7
7
CH17
CH1
CH9
0(*)
H
H
, 00
CH10
CH18
CH2
1(*)
H
, 00
H
CH11
CH19
CH3
1(*)
CH12
CH20
CH4
1(*)
109
EXMF
CH13
CH21
CH5
H
.
CH14
CH22
CH6
SLM
CH15
CH23
CH7
DLC
MFBS
CH16
CH24
CH8
0
0
PEB 2035
(06)
(07)
(08)
(09)