peb2035 ETC-unknow, peb2035 Datasheet - Page 79

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

XSIS … Spare Bit For International Use
XRA … Transmit Remote Alarm
XY0 … XY4 … Spare Bits For National Use (Y-Bits, S
Transmit Spare Bits (WRITE)
Value after RESET: 00
XSP
MXMB … Interrupt Mask: Transmit Multiframe Begin
MRMB … Interrupt Mask: Receive Multiframe Begin
TT0 … Time-Slot 0 Transparent Mode
Semiconductor Group
0 … Normal operation.
1 … Send remote alarm towards remote end by setting bit 3 of the service word.
n
0 … Normal operation.
1 … All information of time-slot 0 at port XDI will be inserted in the outgoing pulseframe. All
First bit of the service word. Only significant in doubleframe format. If not used, this bit
should be fixed to ‘1’. If one of the time-slot 0 transparent modes is enabled (bit XSP.TT0,
XSP.TT0S or EMOD.TT0X), bit XSW.XSIS will be ignored.
If time-slot 0 transparent mode is enabled via bit XSP.TT0, bit XSW.XRA will be ignored.
These bits are inserted in the service word of every other pulseframe if Sn-bit stack mode is
disabled (MODE.ENSN = 0). If not used, they should be fixed to ‘1’.
If one of the time-slot 0 transparent modes is enabled (bit XSP.TT0, XSP.TT0S or
EMOD.TT0X), bits XSW.XY0 … 4 will be ignored.
If the alarm interrupt mode is enabled via bit CCR.AINT, these mask bits select transmit and
receive multiframe begin as interrupt sources (applicable to doubleframe and CRC
multiframe structure):
Mask bit = 0: interrupt source disabled.
Mask bit = 1: interrupt source enabled.
Assigned multiframe status will cause an interrupt signal at port AINT. Acknowledging is
done by writing a ‘1’ to the bit LOOP.AIA or with a read/write access to the assigned Sn-bit
stack address (refer to bits RSP.XFLG and RSP.RFLG). Triggering a new interrupt by the
same source is only possible after this source became inactive.
internal information of the ACFA (framing, CRC, S
ignored. This function is mainly useful for system test applications (test loops).
Priority sequence of transparent modes: XSP.TTO > EMOD.TT0X > XSP.TT0S.
7
MXMB MRMB
H
TT0
TT0S
79
AXS
n
-Bits, S
n
/S
XSIF
i
bit signaling, remote alarm) will be
a
-Bits)
XS13
XS15
0
PEB 2035
(05)