peb2035 ETC-unknow, peb2035 Datasheet - Page 36

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

For transmit direction, contents of time-slot 0 are additionally determined by the selected
transparent mode:
Transparent
Mode
–
XSP.TT0
XSP.TTOS
EMOD.TT0X
Notes:
1) The S
2) Additionally, automatic transmission of submultiframe error indication is selectable.
The CRC procedure is automatically invoked when the multiframe structure is enabled. CRC errors
in the received data stream are counted by the CRC Error Counter CEC (one error per
submultiframe, maximum). This 8-bit counter is extendable to 10-bit length (XSP.AXS, CECX).
As an extension of the alarm interrupt capabilities, the occurrence of a CRC error can be defined as
interrupt source (XC1.MCA) for triggering interrupt port AINT.
Synchronization Procedure
Multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged
at bit RSR.LOS and bit RSR.CAL).
The multiframe resynchronization procedure starts when Doubleframe alignment has been
regained. For Doubleframe synchronization refer to section Doubleframe Format. It may also be
invoked by the user by setting
– bit CCR.FRS for complete Doubleframe and multiframe re-synchronization
– bit MODE.MFCS for multiframe re-synchronization only.
The CRC checking mechanism will be enabled after the first correct multiframe pattern has been
found. However, CRC errors will not be counted in asynchronous state.
The (multiframe) synchronous state is reached after detecting two correct multiframe alignment
patterns at an interval of n
the multiframe pattern is disabled when the receiver is in the synchronous state.
Automatic Force Resynchronization
As addition, a search for Doubleframe alignment is automatically initiated if two multiframe pattern
with a distance of n
alignment has been regained (bit MODE.AFR).
S
Due to new signaling procedures using the five S
multiframe structure, two possibilities of access via the microprocessor are implemented.
Semiconductor Group
a
- Bit Access
a
-bit stack XSN may be used optionally.
Framing + CRC A Bit
(int. generated)
via pin XDI
(int. generated)
(int. generated)
2 ms have not been found within a time interval of 8 ms after doubleframe
2 ms (n = 1,2,3 …). The CRC4 flag RSR.CAL will be reset. Checking
XSW.XRA
via pin XDI
XSW.XRA
XSW.XRA
Source for
36
a
S
XSW.XY0..4
via pin XDI
via pin XDI
via pin XDI
bits (S
n
Bits
a4
… S
1)
a8
) of every other frame of the CRC
E Bits
XSP.XS13/XS15
via pin XDI
via pin XDI
XSP.XS13/XS15
PEB 2035
2)
2)