peb2035 ETC-unknow, peb2035 Datasheet - Page 115

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

FRES ... Freeze Signaling Status
RPE ... Receive Parity Error
XPE ... Transmit Parity Error
XSLP ... Transmit Slip Indication
Multiframe Status Register (READ)
MFR
DSLP ... DMA Request Slip
Semiconductor Group
Some of these alarm indications are simulated only if the ACFA is configured in the
appropriate mode. At simulation steps 0, 3, 4, and 7, pending status flags are reset
automatically and clearing of the error counters is enabled. Incrementing the simulation
counter should not be done at time intervals shorter than 1.5 ms (F4, F12, F72) or 3 ms
(ESF). Otherwise, reactions of initiated simulations may occur at later steps.
Synchronization status signal which informs the CAS-processor that current signaling
should be frozen. Set by:
–
–
–
Cleared after receiving a correct multiframe in the synchronous state.
Set after a receive parity error occurs in the channel selected by register CPY. Cleared by
setting bit CCR.CLR.
The bit will be set during alarm simulation and must be cleared by setting bit CCR.CLR.
Set after a transmit parity error occurs in the channel selected by register CPY. Cleared by
setting bit CCR.CLR.
The bit will be set during alarm simulation and must be cleared by setting bit CCR.CLR.
A one in this bit position indicates that there is an error in the host clock system. If the
wander of the transmit route clock (XRCLK), which normally has to be phase locked to a
common submultiple of the system clock (SCLK) such as 8 kHz, is too great, data
transmission errors will occur. In that case, the transmit speech memory has to be reset to
its start position by writing the initial value to the transmit time-slot counter XC1.XTO.
ASR.XSLP will be reset by bit CCR.CLR.
If the use of the signaling stacks RSIG and XSIG is enabled by setting bit XC0.ISIG, this flag
is set if access to one of these stacks (3 bytes) is not completed before a new assigned
request occurs. The flag is cleared by setting bit CCR.CLR.
one or more framing bit errors in a multiframe
loss of synchronization
receive slip
7
1
1
DSLP
GPE
115
RRS
RMB
XRS
XMB
0
PEB 2035
(05)