peb2035 ETC-unknow, peb2035 Datasheet - Page 27

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Figure 3
The Receive Speech Memory as Circularly Organized Memory
Additionally in PCM 30 mode the receive speech memory can be switched to one frame length
(LOOP.SFM). This feature is useful for master-slave applications to reduce the delay between line
interface and system interface. For correct operation, System Clock SCLK and Synchronous Pulse
SYPQ have to be derived from the Receive Route Clock RRCLK and the Receive Frame
Synchronous Pulse RFSPQ (PLL application). In single frame mode, however, it is not possible to
perform a slip after the slip condition has been detected. Thus, values of receive time-slot/clock-slot
offset (RC0, RC1) have to be specified great enough to prevent too great approach of frame begin
(line side) and frame begin (system side).
Semiconductor Group
S+,
S-
W
R
Frame
:
:
:
Write Pointer (Route Clock controlled)
Read Pointer (System Clock controlled)
Limits for Slip Detection (mode dependent)
2 Time Slots
W
S-
(24) (1)
31
(1) (24)
0
27
R’
R
31
0
S+
Slip
Frame
Moment of Slip Detection
1 Time Slots
ITD03523
PEB 2035