at89c51re2-slsem ATMEL Corporation, at89c51re2-slsem Datasheet - Page 102

• Manufacturer Part Number: at89c51re2-slsem
• Description: At89c51re2 8-bit Flash Microcontroller
• Manufacturer: ATMEL Corporation

7663B–8051–03/07
Table 62. SCON_0 register
SCON_0 - Serial Control Register for UART 0(98h)
Reset Value = 0000 0000b
Bit addressable
FE/SM0_0
Number
7
Bit
7
6
5
4
3
2
1
0
SM1_0
Mnemonic
6
SM0_0
SM1_0
SM2_0
REN_0
RB8_0
TB8_0
FE_0
RI_0
TI_0
Bit
SM2_0
5
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
Serial port Mode bit 0
Refer to SM1_0 for serial port mode selection.
SMOD0_0 must be cleared to enable access to the SM0_0 bit.
Serial port Mode bit 1
SM0SM1ModeDescriptionBaud Rate
0
0
1
1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2_0 = 0, RB8 is the received stop bit. In mode 0 RB8 is
not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 22.
and Figure 23. in the other modes.
0
1
0
1
0Shift RegisterF
18-bit UARTVariable
29-bit UARTF
39-bit UARTVariable
REN_0
4
CPU PERIPH
CPU PERIPH
TB8_0
3
/32 or /16
/6
RB8_0
2
TI_0
1
RI_0
0
85