at89c51re2-slsem ATMEL Corporation, at89c51re2-slsem Datasheet - Page 41

• Manufacturer Part Number: at89c51re2-slsem
• Description: At89c51re2 8-bit Flash Microcontroller
• Manufacturer: ATMEL Corporation

Loading the Column Latches
7663B–8051–03/07
Any number of data from 0 byte to 128 bytes can be loaded in the column latches. The
data written in the column latches can be written in a none consecutive order. The
DPTR allows to select the address of the byte to load in the column latches.
The page address to be written (target page in FM0) is given by the last address loaded
in the column latches and when this page belongs to the upper 32K bytes of the logical
addressable MCU space, the target memory bank selection is performed upon the
MBO2:0 value during the last address loaded.
When 0 byte is loaded in the column latches the activation sequence ( 5xh, Axh in
FCON) does not launch any operations. The FSE bit in FSTA register is set.
When a current flash write operation is on-going (FBUSY is set), it is impossible to load
the columns latches before the end of flash programming process (the write operation in
the columns latches is not performed, and the previous columns latches content is not
overwritten).
When programming is launched, an automatic erase of the entire memory page is first
performed, then programming is effectively done. Thus no page or block erase is
needed and only the loaded data are programmed in the corresponding page. The
unloaded data of the target memory page are programmed at 0xFF value (automatic
page erase value).
The following procedure is used to load the column latches and is summarized in
Figure 4:
•
•
•
•
•
•
•
•
•
Disable interrupt and map the column latch space by setting FPS bit.
Select the target memory bank (for page address larger than 32K)
Map the column latch
Reset the column latch
Load the DPTR with the address to write.
Load Accumulator register with the data to write.
Execute the MOVX @DPTR, A instruction, and only this one (no MOVX @Ri, A).
If needed loop the last three instructions until the page is completely loaded.
Unmap the column latch if needed (it can be left mapped) and Enable Interrupt
41