at89c51re2-slsem ATMEL Corporation, at89c51re2-slsem Datasheet - Page 136

• Manufacturer Part Number: at89c51re2-slsem
• Description: At89c51re2 8-bit Flash Microcontroller
• Manufacturer: ATMEL Corporation

Figure 36. Data Transmission Format (CPHA = 0)
Figure 37. Data Transmission Format (CPHA = 1)
Figure 38. CPHA/SS Timing
Queuing transmission
7663B–8051–03/07
MOSI (from Master)
SCK Cycle Number
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 0)
SCK (CPOL = 1)
MISO (from Slave)
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
Capture Point
SPEN (Internal)
SS (to Slave)
Capture Point
SS (to Slave)
MISO/MOSI
(CPHA = 0)
(CPHA = 1)
Master SS
Slave SS
Slave SS
As shown in Figure 36, the first SCK edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 38).
Figure 37 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmis-
sions (Figure 38). This format may be preferred in systems having only one Master and
only one Slave driving the MISO data line.
For an SPI configured in master or slave mode, a queued data byte must be transmit-
ted/received immediately after the previous transmission has completed.
MSB
MSB
MSB
1
MSB
1
2
bit6
bit6
2
bit6
Byte 1
bit6
3
bit5
bit5
3
bit5
bit5
bit4
4
bit4
bit4
4
bit4
Byte 2
bit3
bit3
5
bit3
bit3
5
6
bit2
bit2
6
bit2
bit2
Byte 3
7
bit1
bit1
7
bit1
bit1
LSB
8
LSB
LSB
8
LSB
119