at89c51re2-slsem ATMEL Corporation, at89c51re2-slsem Datasheet - Page 96

• Manufacturer Part Number: at89c51re2-slsem
• Description: At89c51re2 8-bit Flash Microcontroller
• Manufacturer: ATMEL Corporation

Automatic Address
Recognition
7663B–8051–03/07
Given Address
Figure 22. UART Timings in Mode 1
Figure 23. UART Timings in Modes 2 and 3
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, the user may enable the automatic address recognition feature in mode 1.In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SMOD0=X
SMOD0=1
SMOD0=0
SMOD0=1
SMOD0=1
RXD
RXD
FE
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
RI
FE
RI
RI
Start
bit
Start
bit
D0
D0
D1
D1
D2
D2
D3
Data byte
D3
Data byte
D4
D4
D5
D5
D6
D6
D7
D7
Stop
bit
Ninth
D8
bit
Stop
bit
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