at89c51re2-slsem ATMEL Corporation, at89c51re2-slsem Datasheet - Page 137
at89c51re2-slsem
Manufacturer Part Number
at89c51re2-slsem
Description
At89c51re2 8-bit Flash Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT89C51RE2-SLSEM.pdf
(167 pages)
- Current page: 137 of 167
- Download datasheet (2Mb)
Figure 39. Queuing Transmission In Master Mode
120
MOSI
MISO
Data
SPTE
SCK
AT89C51RE2
MSB
MSB
Byte 1
B6
B6
BYTE 1 under transmission
B5
B5
B4
B4
When a transmission is in progress a new data can be queued and sent as soon as
transmission has been completed. So it is possible to transmit bytes without latency,
useful in some applications.
The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that
the user application can write SPDAT with the data to be transmitted until the SPTE
becomes cleared.
Figure 39 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is
immediately sent on the bus. Meanwhile an other byte is prepared (and the SPTE is
cleared), it will be sent at the end of the current transmission. The next data must be
ready before the end of the current transmission.
In slave mode it is almost the same except it is the external master that start the
transmission.
Also, in slave mode, if no new data is ready, the last value received will be the next data
byte transmitted.
B3
B3
B2
B2
B1
B1
Byte 2
LSB
LSB MSB
MSB
B6
B6
BYTE 2 under transmission
B5
B5
B4
B4
B3
B3
Byte 3
B2
B2
B1
B1
LSB
LSB
7663B–8051–03/07
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