sta003t STMicroelectronics, sta003t Datasheet - Page 10

• Manufacturer Part Number: sta003t
• Description: Mpeg 2.5 Layer Iii Audio Decoder
• Manufacturer: STMicroelectronics

STA003T
Figure 10. Read Mode Sequence
3.4 - READ OPERATION (see Fig. 10)
3.4.1 - Current byte address read
The STA003T has an internal byte address
counter. Each time a byte is written or read, this
counter is incremented.
For the current byte address read mode, follow-
ing a START condition the master sends the de-
vice address with the RW bit set to 1.
The STA003T acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOP condition.
3.4.2 - Sequential address read
This mode can be initiated with either a current
address read or a random address read. How-
ever in this case the master does acknowledge
the data byte output and the STA003T continues
to output the next byte in sequence.
To terminate the streams of bytes the master
I
10/32
2
0x00
0x01
0x05
0x06
0x07
0x0B
0x0C
0x0D
0x0F
C REGISTERS
SEQUENTIAL
SEQUENTIAL
CURRENT
ADDRESS
ADDRESS
CURRENT
HEX_COD
RANDOM
RANDOM
READ
READ
READ
READ
START
START
START
START
DEV-ADDR
DEV-ADDR
DEV-ADDR
DEV-ADDR
DEC_COD
11
12
13
15
6
7
0
1
5
HIGH
RW=
RW
RW
RW
ACK
ACK
ACK
ACK
VERSION
IDENT
PLLCTL [7:0]
PLLCTL_M
PLLCTL_N
reserved
reserved
SCLK_POL
ERROR_CODE
SUB-ADDR
SUB-ADDR
DATA
DATA
NO ACK
ACK
ACK
ACK
START
START
STOP
DATA
DESCRIPTION
DEV-ADDR
DEV-ADDR
RW
RW
does not acknowledge the last received byte, but
terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after one byte output.
4 - I
The following table gives a description of the
MPEG Source Decoder (STA003T) register list.
The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the descrip-
tion of the information contained in the register.
The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the default is "undefined".
The fifth column (R/W) is the flag to distinguish
register "read only" and "read and write", and the
useful size of the register itself.
Each register is 8 bit wide. The master shall oper-
ate reading or writing on 8 bits only.
ACK
ACK
ACK
2
C REGISTERS
DATA
DATA
DATA
NO ACK
NO ACK
ACK
STOP
STOP
DATA
RESET
D98AU826A
0xAC
0x0C
0x21
0x00
0x04
0x00
ACK
DATA
R/W (8)
R/W (8)
R/W (8)
R/W (8)
R (8)
R (8)
R (8)
R/W
NO ACK
STOP