sta003t STMicroelectronics, sta003t Datasheet - Page 18

• Manufacturer Part Number: sta003t
• Description: Mpeg 2.5 Layer Iii Audio Decoder
• Manufacturer: STMicroelectronics

STA003T
DRA
Address: 0x48
Type: R/W
Software Reset: 0X00
Hardware Reset: 0X00
DRA register is used to attenuate the level of
audio output at the Right Channel using the but-
terfly shown in Fig. 11. When the register is set to
DRB
Address: 0x49
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
DRB register is used to re-direct the Right Chan-
nel on the Left, or to mix both the Channels.
PCMDIVIDER
Address: 0x54
Type: RW
Software Reset: 0x01
Hardware Reset: 0x01
PCMDIVIDER is used to set the frequency ratio
between the OCLK (Oversampling Clock for
18/32
PD7
DRA7
DRB7
MSB
MSB
7
b7
b7
0
0
0
0
0
0
0
0
:
:
PD6
6
DRA6
DRB6
b6
b6
0
0
0
1
0
0
0
1
:
:
PD5
5
PD4
DRA5
DRB5
4
b5
b5
0
0
0
1
0
0
0
1
:
:
PD3
3
DRA4
DRB4
b4
b4
0
0
0
0
0
0
0
0
:
:
PD2
2
DRA3
DRB3
PD1
b3
b3
1
0
0
0
0
0
0
0
0
:
:
PD0
0
DRA2
DRB2
b2
b2
0
0
0
0
0
0
0
0
:
:
255
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
Default value is 0x00, corresponding at the maxi-
mum attenuation in the re-direction channel.
DACs), and the SCKT (Serial Audio Transmitter
Clock).
The relation is the following:
DRA1
DRB1
b1
b1
0
0
1
0
0
0
1
0
:
:
(0xFF),
SCKT_freq
DRA0
DRB0
LSB
LSB
b0
b0
0
1
0
0
0
1
0
0
:
:
the
2 1
maximum
OUTPUT ATTENUATION
OUTPUT ATTENUATION
NO ATTENUATION
NO ATTENUATION
OCLK_freq
PCMDIVIDER
Description
Description
-96dB
-96dB
-1dB
-2dB
-1dB
-2dB
:
:
attenuation
is