sta003t STMicroelectronics, sta003t Datasheet - Page 12

• Manufacturer Part Number: sta003t
• Description: Mpeg 2.5 Layer Iii Audio Decoder
• Manufacturer: STMicroelectronics

STA003T
4.1 - STA003T REGISTERS DESCRIPTION
The STA003T device includes 128 I
In this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be ac-
cessed (in Read or in Write mode). The Read-
Only registers must never be written.
The following table describes the meaning of the
abbreviations used in the I2C registers descrip-
tion:
VERSION
Address: 0x00
Type: RO
The VERSION register is read-only and it is used
to identify the IC on the application board.
IDENT
Address: 0x01
Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
IDENT is a read-only register and is used to iden-
tify the IC on an application board. IDENT always
has the value "0xAC"
PLLCTL
Address: 0x05
Type: R/W
12/32
MSB
MSB
V8
b7
b7
1
Symbol
R/WS
UND
R/W
WO
NC
RO
NA
V7
b6
b6
0
b5
V6
b5
1
V5
b4
b4
Read, Write in specific mode
0
Read and Write
V4
b3
b3
Not Applicable
1
No Charge
Read Only
Comment
Undefined
Write Only
V3
b2
b2
1
2
C registers.
b1
V2
b1
0
LSB
LSB
V1
b0
b0
0
Software Reset: 0x21
Hardware Reset: 0x21
UPD_FRAC: when is set to 1, updates FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, uses the XTI as in-
put of the divider X instead of VCO output. It is
set to 0 on HW reset.
XTI2DSPCLK: when is set to 1, uses the XTI as
input of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS: when set to 1, the VCO output is dis-
abled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK fre-
quency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is en-
able as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is dis-
abled. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28
(VDD_5/CLK_OUT) is enabled as buffered (4mA)
master clock output (CLK_OUT). It is set to 0 af-
ter autoboot.
PLLCTL_M
Address: 0x06
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL_N
Address: 0x07
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA003T PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA003T, by DSP soft-
ware.
XTO_
MSB
BUF
b7
XTOD
b6
IS
OCLK
EN
b5
SYS2O
CLK
b4
PPLD
b3
IS
XTI2DS
PCLK
b2
XTI2O
CLK
b1
UPD_F
RAC
LSB
b0