sta003t STMicroelectronics, sta003t Datasheet - Page 30

• Manufacturer Part Number: sta003t
• Description: Mpeg 2.5 Layer Iii Audio Decoder
• Manufacturer: STMicroelectronics

STA003T
5.5 DAC RELATED REGISTERS CONFIGURA-
TION
The different DAC registers must be configured
for 48kHz audio frequency: this is the reference
frequency. The STA003T will use these parame-
ters to derivate the register configurations for the
other audio frequencies (32, 24, 16, 12, 8 KHz)
according to the bistream informations.
The STA003T DAC and PLL register must be
configured according to the following steps:
1) OCLK_Freq determination from the DAC over-
2) PCMDIVIDER (0 x 54) register configuration.
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sampling factor O_FAC.
As all STA003T registers must be configured
for 48KHz reference frequency, the OCLK
frquency is:
OCLK_Freq = O_FAC 48KHz
ex: O_FAC = 384, OCLK_Freq = 18.432MHz
The PCMDIVIDER register is used to config-
ure the frequency ratio between OCLK_Freq
and SCKT_Freq:
SCKT_Freq
The SCKT signal is the bit clock for the DAC
serial output. The SCKT frequency depends
on the number of bits to be transmitted to the
DAC during one LRCKT (Left/Right clock)
clock period. These number of bit depends on
the DAC precision (16, 18, 20 or 24bits) and
on the mode that is used to transmit the data
to the DAC (see figure 8). Once the
PCMCONF register is set according to the
DAC requirements, the number of SCKT clock
periods per LRCKT clock period is 16x2 or
32x2.
a) LRCKT_period = 16x2 SCKT_periods
SCKT_Freq = LRCKT_Freq 32 =
=
As the reference audio frequency is 48 KHz,
the previous relation becomes:
48KHz 32 = 48kHz O_FAC (2 (1+ PCMDI-
VIDER))
O_FAC
2
128
256
384
1 PCMDIVIDER
OCLK_Freq
2
OCLK_Freq
12.288MHz
18.432MHz
6.144MHz
at 48KHz
1
OCLK_Freq
PCMDIVIDER
PLLCTL_N
0
0
0
3) Configuration of the PLL registers to set
* MFSDF(X) is the value of the MFSDF(X)(0x61)
* PLLCTL_N is the value of the PLLCTL_N
* PLLCTL_M is the value of the PLLCTL_N
* PLLFRAC (decimal) is the value of the
The following table gives the possible values for
these registers according to different OCLK_Freq
values. Other values can be supported on re-
quest to STMicroelectronics.
PLLCTL_M
1
Consequently:
PCMDIVIDER = (O_FAC/64)-1
ex: O_FAC = 384, PCMCONF[1:0] = 00,
PCMDIVIDER = 5
b) LRCKT_period = 32x2 SCKT_periods
SCKT_Freq = LRCKT_Freq 64 =
=
Consequently:
PCMDIVIDER = (O_FAC/128)-1
OCLK_FREQ to the desired value computed
in step 1.
The PLL configuration in direct relation with
the XTI input clock frequency (14.72 MHz).
OCLK_freq
register.
(0x07) register.
(0x07) register.
PLLFRAC_H and PLLFRAC_L registers as
PLLFRAC
PLLFRAC_L.
14.72MHz
12
12
11
2
PLLCTL_N
1 PCMDIVIDER
OCLK_Freq
=
1
PLLFRAC
23365
23365
34193
PLLCTL_M 1
256
MFSDF X
1
PLLFRAC_H
MFSDF
PLLFRAC
31
15
65536
9
+