is43dr16320b-3dbi Integrated Silicon Solution, Inc., is43dr16320b-3dbi Datasheet - Page 11

• Manufacturer Part Number: is43dr16320b-3dbi
• Description: 512mb X8, X16 Ddr2 Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

programmed. See “Mode Register (MR)” in the next section. The LM command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until tMRD is met.
address inputs determines the bank, and the address inputs select the row. This row will remains active (or open) for accesses until a
bank, and the address provided on address inputs A0–A9 selects the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL
feature, which allows a READ or WRITE command to be issued prior to tRCD(Min) by delaying the actual registration of the
READ/WRITE command to the internal device by AL clock cycles.
and the address provided on inputs A0–A9 selects the starting column location. The value on input A10 determines whether or not
auto precharge is not selected, the row will remain open for subsequent accesses.
to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW,
state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if
precharge period will be determined by the last PRECHARGE command issued to the bank.
be in the idle mode prior to issuing a REFRESH command. This command is nonpersistent, so it must be issued each time a refresh is
IS43DR86400B, IS43/46DR16320B
Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is
effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and
WE# are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress
are not affected.
LOAD MODE (LM)
The mode registers are loaded via bank address and address inputs. The bank address balls determine which mode register will be
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the bank
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same
bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the bank address inputs determine the
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the bank select inputs selects the bank,
auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD(MIN) by delaying the
actual registration of the READ/WRITE command to the internal device by AL clock cycles. Input data appearing on the DQ is written
the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data
transfer in the current bank and does not violate any other timing parameters. After a bank has been precharged, it is in the idle
there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the
REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#‐before‐RAS# (CBR) REFRESH. All banks must
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
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