lh28f160bg-tl Sharp Microelectronics of the Americas, lh28f160bg-tl Datasheet - Page 13

• Manufacturer Part Number: lh28f160bg-tl
• Description: M-bit Smart Flash Memories
• Manufacturer: Sharp Microelectronics of the Americas

The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V
V
high voltage, block contents are protected against
erasure. If block erase is attempted while V
V
block erase for boot blocks requires that the
corresponding if set, that WP# = V
If block erase is attempted to boot block when the
corresponding WP# = V
SR.5 will be set to "1". Block erase operations with
V
should not be attempted.
4.6 Word Write Command
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.
When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.
CC1
PPLK
IH
< RP# < V
, SR.3 and SR.5 will be set to "1". Successful
and V
PP
= V
HH
PPH1/2
produce spurious results and
IL
. In the absence of this
or RP# = V
IH
or RP# = V
IH
, SR.1 and
CC
PP
HH
=
≤
- 13 -
.
Reliable word writes can only occur when V
V
high voltage, memory contents are protected
against word writes. If word write is attempted while
V
be set to "1". Successful word write for boot blocks
requires that the corresponding if set, that WP# =
V
boot block when the corresponding WP# = V
RP# = V
write operations with V
spurious results and should not be attempted.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V
Specification t
suspend latency.
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to V
However, SR.6 will remain "1" to indicate block
erase suspend status.
CC1
PP
IH
or RP# = V
≤ V
and V
PPLK
IH
, SR.1 and SR.4 will be set to "1". Word
, status register bits SR.3 and SR.4 will
PP
WHRH2
= V
HH
. If word write is attempted to
PPH1/2
LH28F160BG-TL/BGH-TL
defines the block erase
IH
. In the absence of this
< RP# < V
HH
produce
CC
IL
OH
OL
or
=
.
.