lh28f160bg-tl Sharp Microelectronics of the Americas, lh28f160bg-tl Datasheet - Page 5

• Manufacturer Part Number: lh28f160bg-tl
• Description: M-bit Smart Flash Memories
• Manufacturer: Sharp Microelectronics of the Americas

1 INTRODUCTION
This datasheet contains LH28F160BG-TL/BGH-TL
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160BG-TL/
BGH-TL flash memories documentation also
includes ordering information which is referenced in
Section 7.
1.1 New Features
Key enhancements of LH28F160BG-TL/BGH-TL
Smart 3 flash memories are :
Note following important differences :
1.2 Product Overview
The LH28F160BG-TL/BGH-TL are high-performance
16 M-bit Smart 3 flash memories organized as
1 024 k-word of 16 bits. The 1 024 k-word of data
is arranged in two 4 k-word boot blocks, six 4 k-
word parameter blocks and thirty-one 32 k-word
main blocks which are individually erasable in-
system. The memory map is shown in Fig. 1.
V
converter, while V
and word write performance. In addition to flexible
erase and program voltages, the dedicated V
gives complete data protection when V
PP
• 2.7 V V
• Enhanced Suspend Capabilities
• Boot Block Architecture
• V
• To take advantage of Smart 3 technology, allow
2.7 V block erase and word write operations.
Designs that switch V
operations should make sure that the V
voltage transitions to GND.
V
at 2.7 V eliminates the need for a separate 12 V
PPLK
PP
connection to 2.7 V or 12 V.
has been lowered to 1.5 V to support
CC
and V
PP
PP
= 12 V maximizes block erase
Write/Erase Operation
PP
off during read
PP
≤ V
PPLK
PP
pin
.
PP
- 5 -
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (3.0 V
V
block can be independently erased 100 000 times.
Block erase suspend mode allows system software
to suspend block erase to read data from, or write
data to any other block.
Writing memory data is performed in word
increments of the device’s 32 k-word blocks
typically within 55 µs, 4 k-word blocks typically
within 60 µs (3.0 V V
suspend mode enables the system to read data
from, or write data to any other flash memory array
location.
The boot block is located at either the top or the
bottom
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 4.9 for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
V
The status register indicates when the WSM’s block
erase or word write operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
CC
IH
.
and V
of
PP
), independent of other blocks. Each
the
address
LH28F160BG-TL/BGH-TL
CC
and V
map
PP
). Word write
in
order
to