lh28f160bg-tl Sharp Microelectronics of the Americas, lh28f160bg-tl Datasheet - Page 3

• Manufacturer Part Number: lh28f160bg-tl
• Description: M-bit Smart Flash Memories
• Manufacturer: Sharp Microelectronics of the Americas

BLOCK ORGANIZATION
This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in
Fig. 1.
Boot Blocks : The two boot blocks are intended to
replace a dedicated boot PROM in a micro-
processor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the V
WP# pins.
BLOCK DIAGRAM
A
0
-A
19
COUNTER
ADDRESS
ADDRESS
BUFFER
LATCH
INPUT
DECODER
DECODER
Y
X
OUTPUT
BUFFER
PP
, RP# and
COMPARATOR
IDENTIFIER
DQ
REGISTER
REGISTER
STATUS
Y GATING
DATA
0
-DQ
- 3 -
MAIN BLOCKS
15
32 k-WORD
31
Parameter Blocks : The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques,
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.
Main Blocks : The reminder is divided into main
blocks for data or code storage. Each 16 M-bit
device contains thirty-one 32 k words (32 768
words) blocks.
BUFFER
INPUT
INTERFACE
COMMAND
MACHINE
the
WRITE
STATE
USER
byte-rewrite
LH28F160BG-TL/BGH-TL
PROGRAM/ERASE
VOLTAGE SWITCH
LOGIC
I/O
functionality
RP#
CE#
WE#
OE#
WP#
V
RY/BY#
V
V
GND
CC
PP
CC
of