attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 54

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

External Interrupts
Pin Change Interrupt
Timing
54
ATtiny13
The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are
configured as outputs. This feature provides a way of generating a software interrupt.
Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSK
Register control which pins contribute to the pin change interrupts. Pin change interrupts
on PCINT5..0 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set
up as indicated in the specification for the MCU Control Register – MCUCR. When the
INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as
long as the pin is held low. Note that recognition of falling or rising edge interrupts on
INT0 requires the presence of an I/O clock, described in “Clock Systems and their Distri-
bution” on page 21. Low level interrupt on INT0 is detected asynchronously. This implies
that this interrupt can be used for waking the part also from sleep modes other than Idle
mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the
required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 21.
An example of timing of a pin change interrupt is shown in Figure 25.
Figure 25. Timing of pin change interrupts
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
LE
pin_lat
D
Q
pin_sync
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
clk
pcint_syn
pcint_setflag
2535G–AVR–01/07
PCIF