attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 67

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

Timer/Counter Timing
Diagrams
2535G–AVR–01/07
and TCNT0 when the counter decrements. The PWM frequency for the output when
using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
At the very start of period 2 in Figure 32 OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
•
•
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set. Figure 33 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 33. Timer/Counter Timing Diagram, no Prescaling
Figure 34 shows the same timing data, but with the prescaler enabled.
TCNTn
(clk
TOVn
clk
clk
I/O
OCR0A changes its value from MAX, like in Figure 32. When the OCR0A value is
MAX the OCn pin value is the same as the result of a down-counting Compare
Match. To ensure symmetry around BOTTOM the OCn value at MAX must
correspond to the result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR0A, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
I/O
Tn
/1)
MAX - 1
f
OCnxPCPWM
MAX
=
----------------- -
N 510
f
clk_I/O
&
BOTTOM
T0
) is therefore
BOTTOM + 1
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