attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 93

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

The ADC Data Register –
ADCL and ADCH
ADLAR = 0
ADLAR = 1
2535G–AVR–01/07
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start
a conversion on a positive edge of the selected trigger signal. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated.
The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in
SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.
Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be dis-
abled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Com-
plete Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the
input clock to the ADC.
Table 39. ADC Prescaler Selections
Bit
Read/Write
Initial Value
Bit
Read/Write
ADPS2
0
0
0
0
1
1
1
1
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
ADC6
ADC8
ADC0
14
14
ADPS1
R
R
R
R
–
6
0
0
6
0
0
1
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
ADPS0
0
1
0
1
0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
ADC2
ADC4
10
10
R
R
R
R
–
2
0
0
–
2
ADC9
ADC1
ADC3
Division Factor
R
R
R
R
9
1
0
0
9
–
1
128
16
32
64
2
2
4
8
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
–
0
ADCH
ADCL
ADCH
ADCL
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