cs5954am Cypress Semiconductor Corporation., cs5954am Datasheet - Page 10

• Manufacturer Part Number: cs5954am
• Description: Usb Controller For Nand Flash
• Manufacturer: Cypress Semiconductor Corporation.

4.5
The CS5954AM has a built-in transceiver that meets USB specification v2.0. The transceiver connects directly to the physical
layer of the USB engine. It is capable of transmitting or receiving serial data at the full speed USB maximum data rate of
12 Mbits/sec. The 16-bit processor has the ability to set up pointers and block sizes in buffer memory for USB transactions.
The CS5954AM controller contains a number of registers that provide overall control and status functions for USB transactions.
The first set of registers is for control and status functions, while the second group is dedicated to specific endpoint functions.
Communication and data flow on the USB is implemented using endpoints. These uniquely identifiable entities are the terminals
of communication flow between a USB host and USB devices. Each USB device is composed of a collection of independently
operating endpoints. Each endpoint has a unique identifier: the endpoint number. (See USB specification v2.0. sec 5.3.1.)
The CS5954AM also includes the CS5954AM BIOS that provides a set of subroutines via interrupt calls for all USB interface
functions required to communicate with a USB host (refer to [Ref. 1] SL11R_BIOS for more information). The CS5954AM BIOS
greatly simplifies the firmware/software development cycle.
4.5.1
The USB Global Control and Status Register allows high-level control. The Global Control and Status Register bits are defined
as follows.
Note:
Document #: 38-08025 Rev. **
4.
• Suspend state should be entered if there is no activity after 3 mS (UA).
• The US and UA bits are automatically cleared after they are read by the CS5954AM processor.
• D15–D4 are the reserved bits, should be written with zeros.
• The CS5954AM BIOS will set the UE = 1 upon reset.
D15
0
Bit C2 =1 must be set from configuration address (0xC006). See section 4.10.1 for CPU control speed.
D15-D4
D0
D1
D2
D3
USB Interface
USB Global Control and Status Register (0xC080: R/W)
D14
0
D13
0
Reserved
UE
UR
US
UA
XIN
D12
0
22 pF
Cin
D11
0
USB Enable = “1,” Overall USB enable/disable bit
USB Reset = “1,” USB received Reset command
USB SOF = “1,” USB received SOF command
USB Activity = “1,” Activity seen
D10
12 MHz, series, 20-pF load
0
Figure 4-2. 12-MHz Crystal Circuit
D9
ADVANCE
INFORMATION
0
Rf
1M
X1
D8
0
D7
0
D6
0
XOUT
[4]
D5
0
D4
0
22 pF
Rs
2.7K
Cout
UA
D3
US
D2
CS5954AM
Page 10 of 44
UR
D1
UE
D0