cs5954am Cypress Semiconductor Corporation., cs5954am Datasheet - Page 13

• Manufacturer Part Number: cs5954am
• Description: Usb Controller For Nand Flash
• Manufacturer: Cypress Semiconductor Corporation.

4.10
The CS5954AM provides software control registers that can be used to configure the chip mode, clock control, read software
version, and software breakpoint control.
4.10.1
The Configuration Register is used to configure the CS5954AM into the appropriate mode, and to select a clock multiplier.
Notes:
Document #: 38-08025 Rev. **
8.
9.
• On the CS5954AM chip set, this bit will be set to zero.
• There is one mode defined in this document: general-purpose IO (GPIO) mode.
• When the XIN input pin is fed with a 12-MHz signal, the software should set C2 to “1” to enable the PLL.
• X_PCLK is a bidirectional pin allowing an additional clock input for PCLK when selected or an observation pin for
• The X_PCLK can be used as the input clock like XIN, but only when mode C2=0, C1=1, C0=0.
• Upon reset, the CS5954AM BIOS will set this register equal to 0x0010 (i.e., C2=0, C1=0, C0=1, PCLK=XIN, RCLK=XIN,
D15
PCLK when OE = “1.”
OE=0, M1–M0=0=GPIO Mode).
0
D6–4 and C2–0 are Clock Configuration bits. These bits select the clock source. The clock may come from an outside pin (XIN or X_PCLK) or it may come from
the PLL multiplier, as indicated in the table.
By default, this bit will be set to zero by the CS5954AM BIOS.
D3
If Clock Disable bit = “1,” this Clock Configuration register can no longer be modified through software writes. It is a “sticky
bit” used to lock the configuration through a write to this bit in the boot prom code.
D2, D1
D0
If Mode Disable bit = “1,” this Configuration register can no longer be modified through software writes. It is a “sticky bit”
used to lock the configuration through a Write to this bit in the boot prom code.
D15-D7
where
PCLK
RCLK
OE
C2
0
0
0
0
1
1
1
1
Processor Control Registers
Configuration Register (0xC006: R/W)
D14
M1
0
0
0
1
1
D13
0
CD
MD
Reserved
is connected to the CS5954AM processor clock.
is the resulting clock that connects to other modules (i.e., USB engine).
when OE = 1, the X_PCLK (pin 59) will become an output pin of the PCLK value.
M1,M0:
C1
D12
0
0
1
1
0
0
1
1
0
D11
M0
0
0
1
0
1
CS5954AM modes are selected as shown here.
should be set to all zeros
D10
C0
0
0
1
0
1
0
1
0
1
D9
ADVANCE
INFORMATION
0
D8
0
X_PCLK
2/3*XIN
2/3*XIN
8/3*XIN
8/3*XIN
PCLK
4*XIN
4*XIN
D7
XIN
0
D6
C2
D5
C1
Reserved
Reserved
Reserved
[9]
Mode
GPIO
D4
C0
RCLK
4*XIN
4*XIN
4*XIN
4*XIN
XIN
XIN
XIN
XIN
CD
D3
M1
D2
CS5954AM
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M0
D1
OE
0
0
0
1
0
0
1
1
MD
[8]
D0