s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 10

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Figures
8
Figure 12.1
Figure 12.2
Figure 12.3
Figure 14.1
Figure 14.2
Figure 14.3
Figure 15.1
Figure 15.2
Figure 16.1
Figure 16.2
Figure 19.1
Figure 21.1
Figure 22.1
Figure 22.2
Figure 22.3
Figure 22.4
Figure 22.5
Figure 22.6
Figure 22.7
Figure 22.8
Figure 22.9
Figure 22.10 Reset Timings...................................................................................................................................98
Figure 22.11 Asynchronous Program Operation Timings: AVD# Latched Addresses..................................................... 100
Figure 22.12 Asynchronous Program Operation Timings: WE# Latched Addresses ...................................................... 101
Figure 22.13 Synchronous Program Operation Timings: WE# Latched Addresses........................................................ 102
Figure 22.14 Synchronous Program Operation Timings: CLK Latched Addresses ......................................................... 103
Figure 22.15 Chip/Sector Erase Command Sequence .............................................................................................. 104
Figure 22.16 Accelerated Unlock Bypass Programming Timing ................................................................................. 105
Figure 22.17 Data# Polling Timings (During Embedded Algorithm) ........................................................................... 105
Figure 22.18 Toggle Bit Timings (During Embedded Algorithm) ................................................................................ 106
Figure 22.19 Synchronous Data Polling Timings/Toggle Bit Timings .......................................................................... 106
Figure 22.20 DQ2 vs. DQ6 .................................................................................................................................. 107
Figure 22.21 Temporary Sector Unprotect Timing Diagram...................................................................................... 107
Figure 22.22 Sector/Sector Block Protect and Unprotect Timing Diagram................................................................... 108
Figure 22.23 Latency with Boundary Crossing........................................................................................................ 108
Figure 22.24 Latency with Boundary Crossing into Program/Erase Bank .................................................................... 109
Figure 22.25 Example of Wait States Insertion ...................................................................................................... 110
Figure 22.26 Back-to-Back Read/Write Cycle Timings ............................................................................................. 111
Figure 25.1
Figure 26.1
Figure 27.1
Figure 27.2
Figure 27.3
Figure 27.4
Figure 27.5
Figure 27.6
Figure 27.7
Figure 27.8
Figure 29.1
Figure 29.2
Figure 29.3
Figure 29.4
Figure 29.5
Figure 29.6
Figure 29.7
Advanced Sector Protection/Unprotection .............................................................................................37
PPB Program/Erase Algorithm .............................................................................................................40
Lock Register Program Algorithm.........................................................................................................43
Synchronous/Asynchronous State Diagram...........................................................................................64
Program Operation ............................................................................................................................70
Erase Operation ................................................................................................................................73
Data# Polling Algorithm .....................................................................................................................81
Toggle Bit Algorithm ..........................................................................................................................83
Maximum Negative Overshoot Waveform .............................................................................................87
Maximum Positive Overshoot Waveform ...............................................................................................87
Test Setup .......................................................................................................................................90
Input Waveforms and Measurement Levels...........................................................................................90
V
CLK Characterization .........................................................................................................................92
CLK Synchronous Burst Mode Read (rising active CLK) ...........................................................................93
CLK Synchronous Burst Mode Read (Falling Active Clock) .......................................................................94
Synchronous Burst Mode Read ............................................................................................................94
8-word Linear Burst with Wrap Around.................................................................................................95
Linear Burst with RDY Set One Cycle Before Data ..................................................................................95
Asynchronous Mode Read with Latched Addresses .................................................................................96
Asynchronous Mode Read...................................................................................................................97
Functional Block Diagram ................................................................................................................. 116
Power-Up Initialization Timing........................................................................................................... 120
Read Operation (ADV# Low)............................................................................................................. 121
Write Operation (ADV# Low) ............................................................................................................ 121
Page Mode Read Operation (ADV# Low)............................................................................................. 122
Burst Mode Read (4-word burst) ....................................................................................................... 123
Burst Mode Write (4-word burst)....................................................................................................... 124
Wired or Wait Configuration.............................................................................................................. 124
Refresh Collision During Read Operation............................................................................................. 125
Refresh Collision During Write Operation ............................................................................................ 126
Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation ........................ 128
Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation .......................... 128
Load Configuration Register.............................................................................................................. 129
Read Configuration Register ............................................................................................................. 130
Wait Configuration (BCR[8] = 0) ....................................................................................................... 133
Wait Configuration (BCR[8] = 1) ....................................................................................................... 133
Wait Configuration During Burst Operation ......................................................................................... 134
CC
Power-up Diagram ......................................................................................................................91
A d v a n c e
S71WS-J Based MCPs
I n f o r m a t i o n
S71WS-J_03_A3 November 28, 2005