s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 130

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

29.2 Software Access
March 9, 2005 CellRam_03_A0
Software access of the configuration registers uses a sequence of asynchronous READ and asyn-
chronous WRITE operations. The contents of the configuration registers can be read or modified
using the software sequence.
The configuration registers are loaded using a four step sequence consisting of two asynchronous
READ operations followed by two asynchronous WRITE operations (see
quence is virtually identical except that an asynchronous READ is performed during the fourth
operation (see
The address used during all READ and WRITE operations is the highest address of the CellularRAM
device being accessed (3FFFFFh for 64Mb); the content at this address is changed by using this
sequence (note that this is a deviation from the CellularRAM specification).
The data value presented during the third operation (WRITE) in the sequence defines whether the
BCR or the RCR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the
data is 0001h, the sequence will access the BCR. During the fourth operation, the data bus is used
to transfer data in to or out of the configuration registers.
The use of the software sequence does not affect the ability to perform the standard (CRE-con-
trolled) method of loading the configuration registers. However, the software nature of this access
mechanism eliminates the need for the control register enable (CRE) pin. If the software mecha-
nism is used, the CRE pin can simply be tied to V
purposes is no longer required.
Software access of the RCR should not be used to enter or exit DPD.
Notes:
1. The WRITE on the third cycle must be CE# controlled.
A d v a n c e
Figure
ADDRESS
LB#/UB#
Figure 29.3 Load Configuration Register
DA TA
WE#
OE#
CE#
29.4). Note that a third READ cycle cancels the access sequence.
ADDRESS
XXXXh
I n f o r m a t i o n
(MAX)
READ
CellularRAM Type 2
ADDRESS
XXXXh
(MAX)
READ
RCR: 0 000h
BCR: 0 001h
ADDRESS
WRITE
(MAX)
SS
1
. The port line often used for CRE control
ADDRESS
CR VALUE
WRITE
(MAX)
DON'T CARE
IN
Figure
29.3). The read se-
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