s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 69

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

14.3
Note: Device is in the default state upon power-up or hardware reset.
14.4
June 24, 2005 S29WS-J_M0_A4
Address Bit
A19
A18
A17
A16
A15
A14
A13
A12
Configuration Register
Reset Command
Programmable
Table 14.4
device functions.
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address
bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the bank to which the system was writing to the read mode.
Once erasure begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence cycles in a program command se-
quence before programming begins (prior to the third cycle). This resets the bank to which the
system was writing to the read mode. If the program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus-
pend-read mode. Once programming begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command se-
quence. Once in the autoselect mode, the reset command must be written to return to the read
mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the
banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Read Mode
Read Mode
Set Device
Wait State
Function
Clock
RDY
shows the address bits that determine the configuration register settings for various
Settings (Binary)
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
Synchronous Mode
00 = Continuous (default)
01 = 8-word linear with wrap around
10 = 16-word linear with wrap around
11 = 32-word linear with wrap around
000 = Data is valid on the 2nd active CLK edge after AVD# transition to V
001 = Data is valid on the 3rd active CLK edge after AVD# transition to V
010 = Data is valid on the 4th active CLK edge after AVD# transition to V
011 = Data is valid on the 5th active CLK edge after AVD# transition to V
100 = Data is valid on the 6th active CLK edge after AVD# transition to V
101 = Data is valid on the 7th active CLK edge after AVD# transition to V
110 = Reserved
111 = Reserved
D a t a
Table 14.4 Configuration Register
S h e e t
S29WS128J/064J
IH
IH
IH
IH
IH
IH
(default)
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